2D MOSFET operation of a fully-depleted bulk MoS2 at quasi-flatband back-gate

M. Najmzadeh, J. P. Duarte, S. Khandelwal, Y. Zeng, C. Hu

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

9 Citations (Scopus)


In this paper, 2D MOSFET operation of a fully-depleted double-gate bulk MoS2 is studied at a quasi-flatband of the back-gate for the first time. Several key device parameters such as equivalent oxide thickness (EOT), carrier concentration, flatband voltage, dielectric constant and carrier mobility were extracted from I-V and C-V characteristics and at room temperature. In a similar operation to the inversion-mode SOI MOSFETs in [1], the backgate was used to keep a sheet of mobile charges on the flake back-side by its quasi-flatband operation at a fixed voltage (0 V). Afterward, the top-gate was used as the active gate to perform mobile charge accumulation or depletion in the channel. Fig. 1 shows the device architecture together with the high frequency R-C equivalent circuit model for this underlap gate architecture. Fig. 2 represents the top-view microscope picture of the fabricated MoS2 bulk MOSFET with a flake thickness of 38 nm, measured by AFM. The fabrication steps include mechanical exfoliation of MoS2 crystals on a 260 nm thick oxidized Si substrate, e-beam lithography to make S/D pads, 50 nm Ni by thermal evaporation and lift-off, gate patterning, high-k/metal-gate stack deposition (1 nm of SiOx by thermal evaporation, 11 nm of ZrO2 by ALD deposition at 105 °C, 30 nm of Ni by thermal evaporation) and lift-off. The measurements were done at room temperature using an Agilent B1500A Semiconductor Parameter Analyzer. Fig. 3 shows its Id-Vg, reporting a subthreshold slope of 110 mV/dec. and Ion/Ioff of ∼1×105, both at Vds=100 mV.

Original languageEnglish
Title of host publication73rd Annual Device Research Conference (DRC 2015)
Subtitle of host publicationconference digest
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages2
ISBN (Electronic)9781467381345, 9781467381352
ISBN (Print)9781467381369
Publication statusPublished - 3 Aug 2015
Externally publishedYes
Event73rd Annual Device Research Conference, DRC 2015 - Columbus, United States
Duration: 21 Jun 201524 Jun 2015


Other73rd Annual Device Research Conference, DRC 2015
Country/TerritoryUnited States


  • Capacitance
  • Capacitance-voltage characteristics
  • Dielectric constant
  • Logic gates
  • Nickel
  • Resistance


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