50 MHz 16-point FFT processor for WLAN applications

N. Weste; M. Bickerstaff; T. Arivoli; P. J. Ryan; J. W. Dalton; D. J. Skellern; T. M. Percival

50 MHz 16-point FFT processor for WLAN applications

N. Weste^*, M. Bickerstaff, T. Arivoli, P. J. Ryan, J. W. Dalton, D. J. Skellern, T. M. Percival

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 μm TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.

Original language	English
Pages (from-to)	457-460
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1997

Cite this

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title = "50 MHz 16-point FFT processor for WLAN applications",

abstract = "This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 μm TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.",

author = "N. Weste and M. Bickerstaff and T. Arivoli and Ryan, {P. J.} and Dalton, {J. W.} and Skellern, {D. J.} and Percival, {T. M.}",

year = "1997",

language = "English",

pages = "457--460",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

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T1 - 50 MHz 16-point FFT processor for WLAN applications

AU - Weste, N.

AU - Bickerstaff, M.

AU - Arivoli, T.

AU - Ryan, P. J.

AU - Dalton, J. W.

AU - Skellern, D. J.

AU - Percival, T. M.

PY - 1997

Y1 - 1997

N2 - This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 μm TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.

AB - This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 μm TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.

UR - http://www.scopus.com/inward/record.url?scp=0030673944&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0030673944

SP - 457

EP - 460

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

SN - 0886-5930

ER -

50 MHz 16-point FFT processor for WLAN applications

Abstract

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