50 MHz 16-point FFT processor for WLAN applications

N. Weste*, M. Bickerstaff, T. Arivoli, P. J. Ryan, J. W. Dalton, D. J. Skellern, T. M. Percival

*Corresponding author for this work

Research output: Contribution to journalArticle

4 Citations (Scopus)


This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 μm TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.

Original languageEnglish
Pages (from-to)457-460
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1997


Cite this

Weste, N., Bickerstaff, M., Arivoli, T., Ryan, P. J., Dalton, J. W., Skellern, D. J., & Percival, T. M. (1997). 50 MHz 16-point FFT processor for WLAN applications. Proceedings of the Custom Integrated Circuits Conference, 457-460.