This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 μm TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 1997|