A 100 GOPS ASP based baseband processor for wireless communication

Ziyuan Zhu; Shan Tang; Yongtao Su; Juan Han; Gang Sun; Jinglin Shi

A 100 GOPS ASP based baseband processor for wireless communication

Ziyuan Zhu, Shan Tang, Yongtao Su, Juan Han, Gang Sun, Jinglin Shi

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

14 Citations (Scopus)

Abstract

This paper presents an ASP (application specific processor) with 512-bit SIMD (Single Instruction Multiple Data) and 192-bit VLIW (Very Long Instruction Word) architecture optimized for wireless baseband processing. It employs optimized architecture and address generation unit to accelerate the kernel algorithms. Based on the ASP, a multi-core baseband processor is developed which can work at 2×2 MIMO and 20 MHz physical bandwidth configuration for LTE inner receiver and meet requirements of Category 3 User Equipment (CAT3 UE). Furthermore, a silicon implementation of the baseband processor with 130nm CMOS technology is presented. Experimental results show that the baseband processor provides 100 GOPS computing ability at 117.6MHz.

Original language	English
Title of host publication	Proceedings - Design, Automation and Test in Europe, DATE 2013
Pages	121-124
Number of pages	4
Publication status	Published - 2013
Event	16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 - Grenoble, France Duration: 18 Mar 2013 → 22 Mar 2013

Other

Other	16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
Country/Territory	France
City	Grenoble
Period	18/03/13 → 22/03/13

Keywords

AGU
Application specific processor
Baseband processor
LTE
VLIW

Cite this

@inproceedings{f4ab35e2f2ce4151b796dc9fb8c5fb8d,

title = "A 100 GOPS ASP based baseband processor for wireless communication",

abstract = "This paper presents an ASP (application specific processor) with 512-bit SIMD (Single Instruction Multiple Data) and 192-bit VLIW (Very Long Instruction Word) architecture optimized for wireless baseband processing. It employs optimized architecture and address generation unit to accelerate the kernel algorithms. Based on the ASP, a multi-core baseband processor is developed which can work at 2×2 MIMO and 20 MHz physical bandwidth configuration for LTE inner receiver and meet requirements of Category 3 User Equipment (CAT3 UE). Furthermore, a silicon implementation of the baseband processor with 130nm CMOS technology is presented. Experimental results show that the baseband processor provides 100 GOPS computing ability at 117.6MHz.",

keywords = "AGU, Application specific processor, Baseband processor, LTE, VLIW",

author = "Ziyuan Zhu and Shan Tang and Yongtao Su and Juan Han and Gang Sun and Jinglin Shi",

year = "2013",

language = "English",

isbn = "9783981537000",

pages = "121--124",

booktitle = "Proceedings - Design, Automation and Test in Europe, DATE 2013",

note = "16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 ; Conference date: 18-03-2013 Through 22-03-2013",

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TY - GEN

T1 - A 100 GOPS ASP based baseband processor for wireless communication

AU - Zhu, Ziyuan

AU - Tang, Shan

AU - Su, Yongtao

AU - Han, Juan

AU - Sun, Gang

AU - Shi, Jinglin

PY - 2013

Y1 - 2013

N2 - This paper presents an ASP (application specific processor) with 512-bit SIMD (Single Instruction Multiple Data) and 192-bit VLIW (Very Long Instruction Word) architecture optimized for wireless baseband processing. It employs optimized architecture and address generation unit to accelerate the kernel algorithms. Based on the ASP, a multi-core baseband processor is developed which can work at 2×2 MIMO and 20 MHz physical bandwidth configuration for LTE inner receiver and meet requirements of Category 3 User Equipment (CAT3 UE). Furthermore, a silicon implementation of the baseband processor with 130nm CMOS technology is presented. Experimental results show that the baseband processor provides 100 GOPS computing ability at 117.6MHz.

AB - This paper presents an ASP (application specific processor) with 512-bit SIMD (Single Instruction Multiple Data) and 192-bit VLIW (Very Long Instruction Word) architecture optimized for wireless baseband processing. It employs optimized architecture and address generation unit to accelerate the kernel algorithms. Based on the ASP, a multi-core baseband processor is developed which can work at 2×2 MIMO and 20 MHz physical bandwidth configuration for LTE inner receiver and meet requirements of Category 3 User Equipment (CAT3 UE). Furthermore, a silicon implementation of the baseband processor with 130nm CMOS technology is presented. Experimental results show that the baseband processor provides 100 GOPS computing ability at 117.6MHz.

KW - AGU

KW - Application specific processor

KW - Baseband processor

KW - LTE

KW - VLIW

UR - http://www.scopus.com/inward/record.url?scp=84885642692&partnerID=8YFLogxK

M3 - Conference proceeding contribution

AN - SCOPUS:84885642692

SN - 9783981537000

SP - 121

EP - 124

BT - Proceedings - Design, Automation and Test in Europe, DATE 2013

T2 - 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013

Y2 - 18 March 2013 through 22 March 2013

ER -

A 100 GOPS ASP based baseband processor for wireless communication

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