A 14-mW PLL-less receiver in 0.18-μm CMOS for Chinese electronic toll collection standard

Xiaofeng He*, Xi Zhu, Lian Duan, Yichuang Sun, Chengyan Ma

*Corresponding author for this work

Research output: Contribution to journalArticle

33 Citations (Scopus)

Abstract

The design of a 14-mW receiver without phase-locked loop for the Chinese electronic toll collection (ETC) system in a standard 0.18-μm CMOS process is presented in this brief. Since the previously published work was mainly based on vehicle-powered systems, low power consumption was not the primary goal of such a system. In contrast, the presented system is designed for a battery-powered system. Utilizing the presented receiver architecture, the entire receiver only consumes 7.8 mA, at the supply voltage of 1.8 V, which indicates a power saving of at least 38% compared with other state-of-the-art designs for the same application. To verify the performance, the bit error rate is measured to be better than 10-6, which well satisfies the Chinese ETC standard. Moreover, the sensitivity of the designed receiver can be readjusted to -50 dBm, which is required by the standard.

Original languageEnglish
Article number2345303
Pages (from-to)763-767
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume61
Issue number10
DOIs
Publication statusPublished - 1 Oct 2014

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