A 3-5 GHz LNA in 0.25μm SOI CMOS process for implantable WBANs

Ayobami Iji; Xi Zhu; Michael Heimlich

doi:10.1109/MWSCAS.2012.6292133

A 3-5 GHz LNA in 0.25μm SOI CMOS process for implantable WBANs

Ayobami Iji^*, Xi Zhu, Michael Heimlich

^*Corresponding author for this work

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

12 Citations (Scopus)

Abstract

A low-voltage, low-power single-ended LNA is implemented in a 0.25μm SOI CMOS technology. A theoretical basis for the design is used to develop design constraints in conjunction with a layout-aware design flow providing early insight into parasitic effects. The SOI CMOS LNA has a post-layout simulated noise figure of less than 3 dB; input IP3 of -10 dBm and small-signal gain of 19.2 dB within the 3-5 GHz band. Total current consumption is 5.2 mA from 1.5 V supply voltage. The LNA can also operate under a 1V supply voltage with relatively small linear performance degradation. The chip area is 0.89 mm ². Due to the high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, the SOI CMOS technology offers significant performance improvements for LNAs, which makes the designed LNA well suitable for implantable WBANs.

Original language	English
Title of host publication	2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Place of Publication	Piscataway, N.J
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	766-769
Number of pages	4
ISBN (Electronic)	9781467325271
ISBN (Print)	9781467325264
DOIs	https://doi.org/10.1109/MWSCAS.2012.6292133
Publication status	Published - 2012
Event	2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 - Boise, ID, United States Duration: 5 Aug 2012 → 8 Aug 2012

Other

Other	2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Country/Territory	United States
City	Boise, ID
Period	5/08/12 → 8/08/12

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10.1109/MWSCAS.2012.6292133

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title = "A 3-5 GHz LNA in 0.25μm SOI CMOS process for implantable WBANs",

abstract = "A low-voltage, low-power single-ended LNA is implemented in a 0.25μm SOI CMOS technology. A theoretical basis for the design is used to develop design constraints in conjunction with a layout-aware design flow providing early insight into parasitic effects. The SOI CMOS LNA has a post-layout simulated noise figure of less than 3 dB; input IP3 of -10 dBm and small-signal gain of 19.2 dB within the 3-5 GHz band. Total current consumption is 5.2 mA from 1.5 V supply voltage. The LNA can also operate under a 1V supply voltage with relatively small linear performance degradation. The chip area is 0.89 mm 2. Due to the high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, the SOI CMOS technology offers significant performance improvements for LNAs, which makes the designed LNA well suitable for implantable WBANs.",

author = "Ayobami Iji and Xi Zhu and Michael Heimlich",

year = "2012",

doi = "10.1109/MWSCAS.2012.6292133",

language = "English",

isbn = "9781467325264",

pages = "766--769",

booktitle = "2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 ; Conference date: 05-08-2012 Through 08-08-2012",

}

Iji, A, Zhu, X & Heimlich, M 2012, A 3-5 GHz LNA in 0.25μm SOI CMOS process for implantable WBANs. in 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012., 6292133, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, N.J, pp. 766-769, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, United States, 5/08/12. https://doi.org/10.1109/MWSCAS.2012.6292133

A 3-5 GHz LNA in 0.25μm SOI CMOS process for implantable WBANs. / Iji, Ayobami; Zhu, Xi; Heimlich, Michael.
2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012. Piscataway, N.J: Institute of Electrical and Electronics Engineers (IEEE), 2012. p. 766-769 6292133.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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AU - Iji, Ayobami

AU - Zhu, Xi

AU - Heimlich, Michael

PY - 2012

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N2 - A low-voltage, low-power single-ended LNA is implemented in a 0.25μm SOI CMOS technology. A theoretical basis for the design is used to develop design constraints in conjunction with a layout-aware design flow providing early insight into parasitic effects. The SOI CMOS LNA has a post-layout simulated noise figure of less than 3 dB; input IP3 of -10 dBm and small-signal gain of 19.2 dB within the 3-5 GHz band. Total current consumption is 5.2 mA from 1.5 V supply voltage. The LNA can also operate under a 1V supply voltage with relatively small linear performance degradation. The chip area is 0.89 mm 2. Due to the high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, the SOI CMOS technology offers significant performance improvements for LNAs, which makes the designed LNA well suitable for implantable WBANs.

AB - A low-voltage, low-power single-ended LNA is implemented in a 0.25μm SOI CMOS technology. A theoretical basis for the design is used to develop design constraints in conjunction with a layout-aware design flow providing early insight into parasitic effects. The SOI CMOS LNA has a post-layout simulated noise figure of less than 3 dB; input IP3 of -10 dBm and small-signal gain of 19.2 dB within the 3-5 GHz band. Total current consumption is 5.2 mA from 1.5 V supply voltage. The LNA can also operate under a 1V supply voltage with relatively small linear performance degradation. The chip area is 0.89 mm 2. Due to the high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, the SOI CMOS technology offers significant performance improvements for LNAs, which makes the designed LNA well suitable for implantable WBANs.

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DO - 10.1109/MWSCAS.2012.6292133

M3 - Conference proceeding contribution

AN - SCOPUS:84867319727

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BT - 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012

PB - Institute of Electrical and Electronics Engineers (IEEE)

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Y2 - 5 August 2012 through 8 August 2012

ER -

A 3-5 GHz LNA in 0.25μm SOI CMOS process for implantable WBANs

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