An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25um silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40×60um. The design utilises two cascaded divideby-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.
|Title of host publication||Microelectronics|
|Subtitle of host publication||Design, Technology, and Packaging III|
|Publication status||Published - 2008|
|Event||Microelectronics: Design, Technology, and Packaging III - Canberra, ACT, Australia|
Duration: 5 Dec 2007 → 7 Dec 2007
|Other||Microelectronics: Design, Technology, and Packaging III|
|Period||5/12/07 → 7/12/07|