A 6-18.5 GHz dynamic frequency divider in 0.25μm SOI CMOS

Leigh Milner*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review


An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25um silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40×60um. The design utilises two cascaded divideby-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.

Original languageEnglish
Title of host publicationMicroelectronics
Subtitle of host publicationDesign, Technology, and Packaging III
Publication statusPublished - 2008
Externally publishedYes
EventMicroelectronics: Design, Technology, and Packaging III - Canberra, ACT, Australia
Duration: 5 Dec 20077 Dec 2007


OtherMicroelectronics: Design, Technology, and Packaging III
CityCanberra, ACT


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