A 6-18.5 GHz dynamic frequency divider in 0.25μm SOI CMOS

Leigh Milner

doi:10.1117/12.758883

A 6-18.5 GHz dynamic frequency divider in 0.25μm SOI CMOS

Leigh Milner^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

Abstract

An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25um silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40×60um. The design utilises two cascaded divideby-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.

Original language	English
Title of host publication	Microelectronics
Subtitle of host publication	Design, Technology, and Packaging III
Volume	6798
DOIs	https://doi.org/10.1117/12.758883
Publication status	Published - 2008
Externally published	Yes
Event	Microelectronics: Design, Technology, and Packaging III - Canberra, ACT, Australia Duration: 5 Dec 2007 → 7 Dec 2007

Other

Other	Microelectronics: Design, Technology, and Packaging III
Country/Territory	Australia
City	Canberra, ACT
Period	5/12/07 → 7/12/07

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10.1117/12.758883

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title = "A 6-18.5 GHz dynamic frequency divider in 0.25μm SOI CMOS",

abstract = "An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25um silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40×60um. The design utilises two cascaded divideby-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.",

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AB - An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25um silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40×60um. The design utilises two cascaded divideby-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.

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T2 - Microelectronics: Design, Technology, and Packaging III

Y2 - 5 December 2007 through 7 December 2007

ER -

A 6-18.5 GHz dynamic frequency divider in 0.25μm SOI CMOS

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