A 6-18.5 GHz dynamic frequency divider in 0.25 mu m SOICMOS - art. no. 679806

Leigh Milner*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

Abstract

An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25 mu m silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40x60 mu m. The design utilises two cascaded divide-by-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.

Original languageEnglish
Title of host publicationMicroelectronics: design, technology, and packaging III
EditorsAJ Hariz, VK Varadan
Place of PublicationWashington, US
PublisherSPIE
Pages79806-79806
Number of pages5
ISBN (Print)9780819469694
Publication statusPublished - 2008
Externally publishedYes
EventConference on Microelectronics - Design, Technology and Packaging III - Canberra, Australia
Duration: 5 Dec 20077 Dec 2007

Publication series

NamePROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE)
PublisherSPIE-INT SOC OPTICAL ENGINEERING
Volume6798
ISSN (Print)0277-786X

Conference

ConferenceConference on Microelectronics - Design, Technology and Packaging III
CountryAustralia
CityCanberra
Period5/12/077/12/07

Cite this

Milner, L. (2008). A 6-18.5 GHz dynamic frequency divider in 0.25 mu m SOICMOS - art. no. 679806. In AJ. Hariz, & VK. Varadan (Eds.), Microelectronics: design, technology, and packaging III (pp. 79806-79806). (PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE); Vol. 6798). Washington, US: SPIE.