A 6-18.5 GHz dynamic frequency divider in 0.25 mu m SOICMOS - art. no. 679806

Leigh Milner

A 6-18.5 GHz dynamic frequency divider in 0.25 mu m SOICMOS - art. no. 679806

Leigh Milner^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

Abstract

An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25 mu m silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40x60 mu m. The design utilises two cascaded divide-by-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.

Original language	English
Title of host publication	Microelectronics: design, technology, and packaging III
Editors	AJ Hariz, VK Varadan
Place of Publication	Washington, US
Publisher	SPIE
Pages	79806-79806
Number of pages	5
ISBN (Print)	9780819469694
Publication status	Published - 2008
Externally published	Yes
Event	Conference on Microelectronics - Design, Technology and Packaging III - Canberra, Australia Duration: 5 Dec 2007 → 7 Dec 2007

Publication series

Name	PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE)
Publisher	SPIE-INT SOC OPTICAL ENGINEERING
Volume	6798
ISSN (Print)	0277-786X

Conference

Conference	Conference on Microelectronics - Design, Technology and Packaging III
Country/Territory	Australia
City	Canberra
Period	5/12/07 → 7/12/07

Cite this

@inproceedings{e794b2d8a554481ab58c256d0d333073,

title = "A 6-18.5 GHz dynamic frequency divider in 0.25 mu m SOICMOS - art. no. 679806",

abstract = "An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25 mu m silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40x60 mu m. The design utilises two cascaded divide-by-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.",

author = "Leigh Milner",

year = "2008",

language = "English",

isbn = "9780819469694",

series = "PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE)",

publisher = "SPIE",

pages = "79806--79806",

editor = "AJ Hariz and VK Varadan",

booktitle = "Microelectronics: design, technology, and packaging III",

address = "United States",

note = "Conference on Microelectronics - Design, Technology and Packaging III ; Conference date: 05-12-2007 Through 07-12-2007",

}

Milner, L 2008, A 6-18.5 GHz dynamic frequency divider in 0.25 mu m SOICMOS - art. no. 679806. in AJ Hariz & VK Varadan (eds), Microelectronics: design, technology, and packaging III. PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE), vol. 6798, SPIE, Washington, US, pp. 79806-79806, Conference on Microelectronics - Design, Technology and Packaging III, Canberra, Australia, 5/12/07.

A 6-18.5 GHz dynamic frequency divider in 0.25 mu m SOICMOS - art. no. 679806. / Milner, Leigh.
Microelectronics: design, technology, and packaging III. ed. / AJ Hariz; VK Varadan. Washington, US: SPIE, 2008. p. 79806-79806 (PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE); Vol. 6798).

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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PY - 2008

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AB - An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25 mu m silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40x60 mu m. The design utilises two cascaded divide-by-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.

M3 - Conference proceeding contribution

SN - 9780819469694

T3 - PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE)

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BT - Microelectronics: design, technology, and packaging III

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PB - SPIE

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T2 - Conference on Microelectronics - Design, Technology and Packaging III

Y2 - 5 December 2007 through 7 December 2007

ER -

A 6-18.5 GHz dynamic frequency divider in 0.25 mu m SOICMOS - art. no. 679806

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