A 60GHz transformer coupled amplifier in 65nm digital CMOS

Michael Boers

doi:10.1109/RFIC.2010.5477356

A 60GHz transformer coupled amplifier in 65nm digital CMOS

Michael Boers^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

39 Citations (Scopus)

Abstract

A three stage transformer coupled amplifier for operation in the 57-64GHz band is presented. The amplifier uses differential capacitive neutralization and low loss transformers to achieve a gain of 30dB at 61GHz. The amplifier has an output compression point of 7.5dBm and a power added efficiency at 1dB compression of 9% at 57GHz. The amplifier has been fabricated in digital CMOS and occupies an area of 0.055mm².

Original language	English
Title of host publication	RFIC 2010
Subtitle of host publication	Proceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium
Place of Publication	Anaheim, California
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	343-346
Number of pages	4
ISBN (Electronic)	9781424462438
ISBN (Print)	9781424462407
DOIs	https://doi.org/10.1109/RFIC.2010.5477356
Publication status	Published - 2010
Externally published	Yes
Event	2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010 - Anaheim, CA, United States Duration: 23 May 2010 → 25 May 2010

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)	1529-2517

Conference

Conference	2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010
Country/Territory	United States
City	Anaheim, CA
Period	23/05/10 → 25/05/10

Keywords

CMOS MMIC
Millimeter-wave amplifier
Power added efficiency
Transformer coupled

Access to Document

10.1109/RFIC.2010.5477356

Cite this

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title = "A 60GHz transformer coupled amplifier in 65nm digital CMOS",

abstract = "A three stage transformer coupled amplifier for operation in the 57-64GHz band is presented. The amplifier uses differential capacitive neutralization and low loss transformers to achieve a gain of 30dB at 61GHz. The amplifier has an output compression point of 7.5dBm and a power added efficiency at 1dB compression of 9% at 57GHz. The amplifier has been fabricated in digital CMOS and occupies an area of 0.055mm2.",

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Boers, M 2010, A 60GHz transformer coupled amplifier in 65nm digital CMOS. in RFIC 2010: Proceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium. Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, Institute of Electrical and Electronics Engineers (IEEE), Anaheim, California, pp. 343-346, 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010, Anaheim, CA, United States, 23/05/10. https://doi.org/10.1109/RFIC.2010.5477356

A 60GHz transformer coupled amplifier in 65nm digital CMOS. / Boers, Michael.
RFIC 2010: Proceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium. Anaheim, California: Institute of Electrical and Electronics Engineers (IEEE), 2010. p. 343-346 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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KW - Power added efficiency

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A 60GHz transformer coupled amplifier in 65nm digital CMOS

Abstract

Publication series

Conference

Keywords

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