A configurable symbol timing recovery based on FPGA with fast convergence to synchronization

As software defined radio (SDR) becomes more prevalent in wireless communications nowadays, a symbol timing recovery (STR) system with configurability of the symbol rate would be required in order to support different wireless standards. Convergence time i.e. how much time needed to achieve a synchronous status during alignment of timing phase, is one of the factors to determine STR performance. In the existing multi-symbol-rate STRs, convergence time varies depending on the moment of the symbol rate switching even without considering noise effect. A longer convergence time results in more initial errors in the symbol decision. This is undesirable because longer preamble bits are required for synchronization thus reducing the throughput rate. This paper presents a configurable STR using digital signal processing (DSP) algorithms, with fast convergence time that can be achieved by searching for the minimum timing error (which occurs at the optimal sampling instant) within each symbol period, and then capturing the associated optimal symbol sample at the zero-crossing of the filtered signal. The convergence time is calculated based on the predefined symbol period regardless the moment of the symbol rate switching. The proposed configurable STR is implemented using Xilinx Virtex-4 FPGA. Implementation results show that at least 21% of the FPGA hardware utilization has been saved for the proposed configurable STR as compared to the existing configurable STRs.