A folded-switching mixer in SOI CMOS technology

Ayobami Iji; Xi Zhu; Michael Heimlich

doi:10.1109/MWSCAS.2012.6292056

A folded-switching mixer in SOI CMOS technology

Ayobami Iji^*, Xi Zhu, Michael Heimlich

^*Corresponding author for this work

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

5 Citations (Scopus)

Abstract

A wideband 3.5 to 5.5GHz low voltage folded-switching mixer is implemented in 0.25um SOI CMOS technology. The post-layout simulation of the designed mixer at 4.5GHz has noise figure (NF) of 9.6dB, input IP3 of -9dBm, conversion gain (CG) of 10.9dB and total current consumption including bias is 4.5mA under 1.5V supply voltage. The designed mixer can also operate under 1V supply voltage with relatively small linear performances degradation. The chip area is 0.55×0.5mm ². Due to high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, SOI CMOS technology offers significant performance improvements for mixers, which makes the designed mixer well suitable for low voltage and low power applications.

Original language	English
Title of host publication	2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Place of Publication	Piscataway, N.J
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	458-461
Number of pages	4
ISBN (Electronic)	9781467325271
ISBN (Print)	9781467325264
DOIs	https://doi.org/10.1109/MWSCAS.2012.6292056
Publication status	Published - 2012
Event	2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 - Boise, ID, United States Duration: 5 Aug 2012 → 8 Aug 2012

Other

Other	2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Country/Territory	United States
City	Boise, ID
Period	5/08/12 → 8/08/12

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10.1109/MWSCAS.2012.6292056

Cite this

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title = "A folded-switching mixer in SOI CMOS technology",

abstract = "A wideband 3.5 to 5.5GHz low voltage folded-switching mixer is implemented in 0.25um SOI CMOS technology. The post-layout simulation of the designed mixer at 4.5GHz has noise figure (NF) of 9.6dB, input IP3 of -9dBm, conversion gain (CG) of 10.9dB and total current consumption including bias is 4.5mA under 1.5V supply voltage. The designed mixer can also operate under 1V supply voltage with relatively small linear performances degradation. The chip area is 0.55×0.5mm 2. Due to high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, SOI CMOS technology offers significant performance improvements for mixers, which makes the designed mixer well suitable for low voltage and low power applications.",

author = "Ayobami Iji and Xi Zhu and Michael Heimlich",

year = "2012",

doi = "10.1109/MWSCAS.2012.6292056",

language = "English",

isbn = "9781467325264",

pages = "458--461",

booktitle = "2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 ; Conference date: 05-08-2012 Through 08-08-2012",

}

Iji, A, Zhu, X & Heimlich, M 2012, A folded-switching mixer in SOI CMOS technology. in 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012., 6292056, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, N.J, pp. 458-461, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, United States, 5/08/12. https://doi.org/10.1109/MWSCAS.2012.6292056

A folded-switching mixer in SOI CMOS technology. / Iji, Ayobami; Zhu, Xi; Heimlich, Michael.
2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012. Piscataway, N.J: Institute of Electrical and Electronics Engineers (IEEE), 2012. p. 458-461 6292056.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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AU - Iji, Ayobami

AU - Zhu, Xi

AU - Heimlich, Michael

PY - 2012

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N2 - A wideband 3.5 to 5.5GHz low voltage folded-switching mixer is implemented in 0.25um SOI CMOS technology. The post-layout simulation of the designed mixer at 4.5GHz has noise figure (NF) of 9.6dB, input IP3 of -9dBm, conversion gain (CG) of 10.9dB and total current consumption including bias is 4.5mA under 1.5V supply voltage. The designed mixer can also operate under 1V supply voltage with relatively small linear performances degradation. The chip area is 0.55×0.5mm 2. Due to high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, SOI CMOS technology offers significant performance improvements for mixers, which makes the designed mixer well suitable for low voltage and low power applications.

AB - A wideband 3.5 to 5.5GHz low voltage folded-switching mixer is implemented in 0.25um SOI CMOS technology. The post-layout simulation of the designed mixer at 4.5GHz has noise figure (NF) of 9.6dB, input IP3 of -9dBm, conversion gain (CG) of 10.9dB and total current consumption including bias is 4.5mA under 1.5V supply voltage. The designed mixer can also operate under 1V supply voltage with relatively small linear performances degradation. The chip area is 0.55×0.5mm 2. Due to high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, SOI CMOS technology offers significant performance improvements for mixers, which makes the designed mixer well suitable for low voltage and low power applications.

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BT - 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012

PB - Institute of Electrical and Electronics Engineers (IEEE)

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T2 - 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012

Y2 - 5 August 2012 through 8 August 2012

ER -

A folded-switching mixer in SOI CMOS technology

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