A fully RNS based ECC processor

Shahzad Asif; Md Selim Hossain; Yinan Kong; Wadood Abdul

doi:10.1016/j.vlsi.2017.11.010

A fully RNS based ECC processor

Shahzad Asif^*, Md Selim Hossain, Yinan Kong, Wadood Abdul

^*Corresponding author for this work

School of Engineering

Research output: Contribution to journal › Article › peer-review

20 Citations (Scopus)

Abstract

This work proposes a residue number system (RNS) based hardware architecture of an elliptic curve cryptography (ECC) processor over prime field. The processor computes point multiplication in Jacobian coordinates by a combined architecture of point doubling and point addition. An optimized modular reduction architecture is also presented that achieves low area by dividing the RNS moduli in small groups and processes the groups one by one. The proposed ECC processor is generic and supports any random curve over Fp256. The implementation on Virtex-7 and Virtex-6 FPGAs shows comparable performance to the state-of-the-art binary and RNS based ECC processors.

Original language	English
Pages (from-to)	138-149
Number of pages	12
Journal	Integration, the VLSI Journal
Volume	61
DOIs	https://doi.org/10.1016/j.vlsi.2017.11.010
Publication status	Published - Mar 2018

Keywords

ECC processor (ECP)
elliptic curve cryptography (ECC)
elliptic curve point multiplication (ECPM)
field programmable gate array (FPGA)
modular multiplier
montgomery multiplier
residue number system (RNS)

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10.1016/j.vlsi.2017.11.010

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@article{ef3ab97accc045caaee4d0f1db691139,

title = "A fully RNS based ECC processor",

abstract = "This work proposes a residue number system (RNS) based hardware architecture of an elliptic curve cryptography (ECC) processor over prime field. The processor computes point multiplication in Jacobian coordinates by a combined architecture of point doubling and point addition. An optimized modular reduction architecture is also presented that achieves low area by dividing the RNS moduli in small groups and processes the groups one by one. The proposed ECC processor is generic and supports any random curve over Fp256. The implementation on Virtex-7 and Virtex-6 FPGAs shows comparable performance to the state-of-the-art binary and RNS based ECC processors.",

keywords = "ECC processor (ECP), elliptic curve cryptography (ECC), elliptic curve point multiplication (ECPM), field programmable gate array (FPGA), modular multiplier, montgomery multiplier, residue number system (RNS)",

author = "Shahzad Asif and Hossain, {Md Selim} and Yinan Kong and Wadood Abdul",

year = "2018",

month = mar,

doi = "10.1016/j.vlsi.2017.11.010",

language = "English",

volume = "61",

pages = "138--149",

journal = "Integration, the VLSI Journal",

issn = "0167-9260",

publisher = "Elsevier",

}

TY - JOUR

T1 - A fully RNS based ECC processor

AU - Asif, Shahzad

AU - Hossain, Md Selim

AU - Kong, Yinan

AU - Abdul, Wadood

PY - 2018/3

Y1 - 2018/3

N2 - This work proposes a residue number system (RNS) based hardware architecture of an elliptic curve cryptography (ECC) processor over prime field. The processor computes point multiplication in Jacobian coordinates by a combined architecture of point doubling and point addition. An optimized modular reduction architecture is also presented that achieves low area by dividing the RNS moduli in small groups and processes the groups one by one. The proposed ECC processor is generic and supports any random curve over Fp256. The implementation on Virtex-7 and Virtex-6 FPGAs shows comparable performance to the state-of-the-art binary and RNS based ECC processors.

AB - This work proposes a residue number system (RNS) based hardware architecture of an elliptic curve cryptography (ECC) processor over prime field. The processor computes point multiplication in Jacobian coordinates by a combined architecture of point doubling and point addition. An optimized modular reduction architecture is also presented that achieves low area by dividing the RNS moduli in small groups and processes the groups one by one. The proposed ECC processor is generic and supports any random curve over Fp256. The implementation on Virtex-7 and Virtex-6 FPGAs shows comparable performance to the state-of-the-art binary and RNS based ECC processors.

KW - ECC processor (ECP)

KW - elliptic curve cryptography (ECC)

KW - elliptic curve point multiplication (ECPM)

KW - field programmable gate array (FPGA)

KW - modular multiplier

KW - montgomery multiplier

KW - residue number system (RNS)

UR - http://www.scopus.com/inward/record.url?scp=85039433203&partnerID=8YFLogxK

U2 - 10.1016/j.vlsi.2017.11.010

DO - 10.1016/j.vlsi.2017.11.010

M3 - Article

AN - SCOPUS:85039433203

SN - 0167-9260

VL - 61

SP - 138

EP - 149

JO - Integration, the VLSI Journal

JF - Integration, the VLSI Journal

ER -

A fully RNS based ECC processor

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