A high PSRR capacitor-less on-chip low dropout voltage regulator

Mohammad Usaid Abbasi, Darren Bagnall, Vishwas Bn

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

6 Citations (Scopus)

Abstract

A design of a high PSRR capacitor-less low dropout voltage regulator (LDO) is presented. This circuit is stable for full load current range from 0 to 100mA. A mid frequency zero has been introduced to stabilize the loop. The PSRR achieved was -71.258dB at 130kHz, and more than -40dB upto 650.750kHz. The LDO is capable of generating fixed 1V from a supply of 3.0V which on discharging goes to 1.5V. The LDO has been implemented in 0.18μm generic CMOS technology. Simulation result showed that the line regulation achieved was 370μV/V and load regulation was just 0.01173%/mA.

Original languageEnglish
Title of host publicationIEEE 8th International Symposium on Intelligent Systems and Informatics
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages361-364
Number of pages4
ISBN (Electronic)9781424473960, 9781424473953
ISBN (Print)9781424473946
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event8th IEEE International Symposium on Intelligent Systems and Informatics - Subotica, Serbia
Duration: 10 Sep 201011 Sep 2010

Publication series

Name
ISSN (Print)1949-047X
ISSN (Electronic)1949-0488

Conference

Conference8th IEEE International Symposium on Intelligent Systems and Informatics
Abbreviated titleSISY 2010
CountrySerbia
CitySubotica
Period10/09/1011/09/10

Keywords

  • Analog circuit design
  • LDO
  • high PSRR
  • capacitorless LDO
  • load regulation
  • line regulation

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