@inproceedings{e5dd590292334b8581dbe19d3021a34c,
title = "A high PSRR capacitor-less on-chip low dropout voltage regulator",
abstract = "A design of a high PSRR capacitor-less low dropout voltage regulator (LDO) is presented. This circuit is stable for full load current range from 0 to 100mA. A mid frequency zero has been introduced to stabilize the loop. The PSRR achieved was -71.258dB at 130kHz, and more than -40dB upto 650.750kHz. The LDO is capable of generating fixed 1V from a supply of 3.0V which on discharging goes to 1.5V. The LDO has been implemented in 0.18μm generic CMOS technology. Simulation result showed that the line regulation achieved was 370μV/V and load regulation was just 0.01173%/mA.",
keywords = "Analog circuit design, LDO, high PSRR, capacitorless LDO, load regulation, line regulation",
author = "Abbasi, {Mohammad Usaid} and Darren Bagnall and Vishwas Bn",
year = "2010",
doi = "10.1109/SISY.2010.5647405",
language = "English",
isbn = "9781424473946",
publisher = "Institute of Electrical and Electronics Engineers (IEEE)",
pages = "361--364",
booktitle = "IEEE 8th International Symposium on Intelligent Systems and Informatics",
address = "United States",
note = "8th IEEE International Symposium on Intelligent Systems and Informatics, SISY 2010 ; Conference date: 10-09-2010 Through 11-09-2010",
}