A high PSRR low dropout voltage regulator with fast settling response

Mohammad Usaid Abbasi, Darren Bagnall, Vishwas Bangayar Nagaraju

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

2 Citations (Scopus)

Abstract

A design of a low dropout voltage regulator (LDO) with fast settling response is being reported. This circuit is stable for full load current range from 0 to 150mA. A current boost circuit is being used to improve the transient response. There was an overshoot of mere 10.51mV and settling time achieved was 43.8ns. The PSRR achieved was -84.464dB upto 8.895kHz, and more than -70db till 136.218MHz. The LDO is capable of generating fixed 1V from a supply of 3.0V which on discharging goes to 1.5V. The LDO has been implemented in 0.18μm generic CMOS technology. Simulation result showed that the line regulation achieved was 174.2μV/Vand load regulation was 0.001626%/mA.

Original languageEnglish
Title of host publication2010 International Conference on Communication Control and Computing Technologies
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages183-186
Number of pages4
ISBN (Electronic)9781424477708, 9781424477685
ISBN (Print)9781424477692
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 IEEE International Conference on Communication Control and Computing Technologies, ICCCCT 2010 - Nagercoil, Tamil Nadu, India
Duration: 7 Oct 20109 Oct 2010

Conference

Conference2010 IEEE International Conference on Communication Control and Computing Technologies, ICCCCT 2010
CountryIndia
CityNagercoil, Tamil Nadu
Period7/10/109/10/10

Keywords

  • Analog circuit design
  • LDO
  • Fast Transient Response
  • load regulation
  • line regulation

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