Abstract
A design of a low dropout voltage regulator (LDO) with fast settling response is being reported. This circuit is stable for full load current range from 0 to 150mA. A current boost circuit is being used to improve the transient response. There was an overshoot of mere 10.51mV and settling time achieved was 43.8ns. The PSRR achieved was -84.464dB upto 8.895kHz, and more than -70db till 136.218MHz. The LDO is capable of generating fixed 1V from a supply of 3.0V which on discharging goes to 1.5V. The LDO has been implemented in 0.18μm generic CMOS technology. Simulation result showed that the line regulation achieved was 174.2μV/Vand load regulation was 0.001626%/mA.
| Original language | English |
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| Title of host publication | 2010 International Conference on Communication Control and Computing Technologies |
| Place of Publication | Piscataway, NJ |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Pages | 183-186 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781424477708, 9781424477685 |
| ISBN (Print) | 9781424477692 |
| DOIs | |
| Publication status | Published - 2010 |
| Externally published | Yes |
| Event | 2010 IEEE International Conference on Communication Control and Computing Technologies, ICCCCT 2010 - Nagercoil, Tamil Nadu, India Duration: 7 Oct 2010 → 9 Oct 2010 |
Conference
| Conference | 2010 IEEE International Conference on Communication Control and Computing Technologies, ICCCCT 2010 |
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| Country/Territory | India |
| City | Nagercoil, Tamil Nadu |
| Period | 7/10/10 → 9/10/10 |
Keywords
- Analog circuit design
- LDO
- Fast Transient Response
- load regulation
- line regulation