A low-cost architecture for DWT filter banks in RNS applications

Yinan Kong, Azadeh Safari, C. V. Niras

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

1 Citation (Scopus)

Abstract

This paper presents a low-cost Finite Impulse Response (FIR) filter architecture for Discrete Wavelet Transform (DWT) using Residue Number System (RNS) arithmetic blocks. Modular adders and multipliers of the RNS-based filter banks are simplified using the low-cost moduli set (2n-1, 2n, 2n+1) and 6-bit dyadic-fraction filter coefficients. The FPGA synthesis results show that the proposed RNS-based filters operate 28% faster than the initial filter banks operated by binary arithmetic. Another noteworthy result is that the proposed RNS-based filter bank require less area compared to the initial filter bank. It confirms that using the proposed architecture for RNS-based filter banks has saved on the hardware complexity and the system area requirement.

Original languageEnglish
Title of host publicationProceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages448-451
Number of pages4
ISBN (Electronic)9781479948338, 9781479948345
ISBN (Print)9781479948321
DOIs
Publication statusPublished - 2014
Event14th International Symposium on Integrated Circuits, ISIC 2014 - Singapore, Singapore
Duration: 10 Dec 201412 Dec 2014

Other

Other14th International Symposium on Integrated Circuits, ISIC 2014
CountrySingapore
CitySingapore
Period10/12/1412/12/14

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  • Cite this

    Kong, Y., Safari, A., & Niras, C. V. (2014). A low-cost architecture for DWT filter banks in RNS applications. In Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014 (pp. 448-451). [7029566] Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ISICIR.2014.7029566