Abstract
This paper presents a low-cost Finite Impulse Response (FIR) filter architecture for Discrete Wavelet Transform (DWT) using Residue Number System (RNS) arithmetic blocks. Modular adders and multipliers of the RNS-based filter banks are simplified using the low-cost moduli set (2n-1, 2n, 2n+1) and 6-bit dyadic-fraction filter coefficients. The FPGA synthesis results show that the proposed RNS-based filters operate 28% faster than the initial filter banks operated by binary arithmetic. Another noteworthy result is that the proposed RNS-based filter bank require less area compared to the initial filter bank. It confirms that using the proposed architecture for RNS-based filter banks has saved on the hardware complexity and the system area requirement.
Original language | English |
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Title of host publication | Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014 |
Place of Publication | Piscataway, NJ |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 448-451 |
Number of pages | 4 |
ISBN (Electronic) | 9781479948338, 9781479948345 |
ISBN (Print) | 9781479948321 |
DOIs | |
Publication status | Published - 2014 |
Event | 14th International Symposium on Integrated Circuits, ISIC 2014 - Singapore, Singapore Duration: 10 Dec 2014 → 12 Dec 2014 |
Other
Other | 14th International Symposium on Integrated Circuits, ISIC 2014 |
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Country/Territory | Singapore |
City | Singapore |
Period | 10/12/14 → 12/12/14 |