A low-cost architecture for DWT filter banks in RNS applications

Yinan Kong; Azadeh Safari; C. V. Niras

doi:10.1109/ISICIR.2014.7029566

A low-cost architecture for DWT filter banks in RNS applications

Yinan Kong, Azadeh Safari, C. V. Niras

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution

1 Citation (Scopus)

Abstract

This paper presents a low-cost Finite Impulse Response (FIR) filter architecture for Discrete Wavelet Transform (DWT) using Residue Number System (RNS) arithmetic blocks. Modular adders and multipliers of the RNS-based filter banks are simplified using the low-cost moduli set (2ⁿ-1, 2ⁿ, 2ⁿ+1) and 6-bit dyadic-fraction filter coefficients. The FPGA synthesis results show that the proposed RNS-based filters operate 28% faster than the initial filter banks operated by binary arithmetic. Another noteworthy result is that the proposed RNS-based filter bank require less area compared to the initial filter bank. It confirms that using the proposed architecture for RNS-based filter banks has saved on the hardware complexity and the system area requirement.

Original language	English
Title of host publication	Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	448-451
Number of pages	4
ISBN (Electronic)	9781479948338, 9781479948345
ISBN (Print)	9781479948321
DOIs	https://doi.org/10.1109/ISICIR.2014.7029566
Publication status	Published - 2014
Event	14th International Symposium on Integrated Circuits, ISIC 2014 - Singapore, Singapore Duration: 10 Dec 2014 → 12 Dec 2014

Other

Other	14th International Symposium on Integrated Circuits, ISIC 2014
Country	Singapore
City	Singapore
Period	10/12/14 → 12/12/14

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10.1109/ISICIR.2014.7029566

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Kong, Y., Safari, A., & Niras, C. V. (2014). A low-cost architecture for DWT filter banks in RNS applications. In Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014 (pp. 448-451). [7029566] Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ISICIR.2014.7029566

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abstract = "This paper presents a low-cost Finite Impulse Response (FIR) filter architecture for Discrete Wavelet Transform (DWT) using Residue Number System (RNS) arithmetic blocks. Modular adders and multipliers of the RNS-based filter banks are simplified using the low-cost moduli set (2n-1, 2n, 2n+1) and 6-bit dyadic-fraction filter coefficients. The FPGA synthesis results show that the proposed RNS-based filters operate 28{\%} faster than the initial filter banks operated by binary arithmetic. Another noteworthy result is that the proposed RNS-based filter bank require less area compared to the initial filter bank. It confirms that using the proposed architecture for RNS-based filter banks has saved on the hardware complexity and the system area requirement.",

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Kong, Y, Safari, A & Niras, CV 2014, A low-cost architecture for DWT filter banks in RNS applications. in Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014., 7029566, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 448-451, 14th International Symposium on Integrated Circuits, ISIC 2014, Singapore, Singapore, 10/12/14. https://doi.org/10.1109/ISICIR.2014.7029566

A low-cost architecture for DWT filter banks in RNS applications. / Kong, Yinan; Safari, Azadeh; Niras, C. V.

Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014. Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE), 2014. p. 448-451 7029566.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution

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AB - This paper presents a low-cost Finite Impulse Response (FIR) filter architecture for Discrete Wavelet Transform (DWT) using Residue Number System (RNS) arithmetic blocks. Modular adders and multipliers of the RNS-based filter banks are simplified using the low-cost moduli set (2n-1, 2n, 2n+1) and 6-bit dyadic-fraction filter coefficients. The FPGA synthesis results show that the proposed RNS-based filters operate 28% faster than the initial filter banks operated by binary arithmetic. Another noteworthy result is that the proposed RNS-based filter bank require less area compared to the initial filter bank. It confirms that using the proposed architecture for RNS-based filter banks has saved on the hardware complexity and the system area requirement.

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