A Multi-Processing Systems-on-Chip native simulation framework for power and thermal-aware design

Daniel Calvo*, Pablo González, Luís Díaz, Héctor Posadas, Pablo Sánchez, Eugenio Villar, Andrea Acquaviva, Enrico MacIi

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


The continuous advance in technology enables the design of more complex embedded systems making use of increasingly powerful Multi-Processing Systems-on-Chip. These new systems can be used in new applications that require increasing performance with lower cost and power consumption and higher reliability. Finding the right compromise among these contradictory constraints makes initial architectural design decisions crucial as they may compromise the quality of the final implementation. In Multi-Processing Systems-on-Chip design, the analysis of chip temperature is becoming increasingly important due to its impact on system reliability, power consumption and cost. In this paper, we propose a complete framework based on native simulation for early estimation of power consumption and thermal flow in Multi-Processing Systems-on-Chip. Native simulation enables fast modeling and simulation of the embedded software running on a specific platform in close interaction with all the platform components. The activity of each component is monitored by using high-level models, which enable the estimation of the power consumed. The power figures feed a high-level Multi-Processing Systems-on-Chip thermal model which supplies chip temperature estimations. At the same time, advanced techniques to manage power and temperature have been modeled. Thus, the proposed framework enables the detection of power and thermal hot spots in the first stages of the design flow, allowing the exploration of different alternatives to address these problems. The framework has been validated by comparing the results provided with an Instruction Set Simulator. The results show around 2% error in the estimations, while simulation time is speeded up three orders of magnitude. Different examples have been developed to demonstrate the capabilities of the proposed methodology in a variety of cases.

Original languageEnglish
Pages (from-to)2-16
Number of pages15
JournalJournal of Low Power Electronics
Issue number1
Publication statusPublished - Feb 2011
Externally publishedYes


  • Design space exploration
  • Low-power
  • Management
  • MPSoC
  • Native Simulation
  • Performance
  • SystemC
  • Temperature


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