Abstract
In this paper, error detection and correction algorithms are studied and a novel approach is proposed to increase the speed of computations using the polynomial residue number system (PRNS) in a Wireless Sensor Network (WSN). The proposed approach employs a Cyclical Redundancy Code (CRC) to reduce the number of gates required in the PRNS. It is compared with a binary number contender in terms of speed, number of gates for adder implementation, propagation delay and power consumption. Comparison results show the competence of the proposed method in comparison with the binary number contender.
Original language | English |
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Title of host publication | Canadian Conference on Electrical and Computer Engineering |
Place of Publication | Piscataway, NJ |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 1-4 |
Number of pages | 4 |
ISBN (Electronic) | 9781479930999 |
DOIs | |
Publication status | Published - 17 Sep 2014 |
Event | 2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering, CCECE 2014 - Toronto, Canada Duration: 4 May 2014 → 7 May 2014 |
Other
Other | 2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering, CCECE 2014 |
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Country/Territory | Canada |
City | Toronto |
Period | 4/05/14 → 7/05/14 |