A phase-locked loop reference spur modelling using simulink

Noorfazila Kamal*, Said Al-Sarawi, Neil H E Weste, Derek Abbott

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

4 Citations (Scopus)

Abstract

Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.

Original languageEnglish
Title of host publication2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages279-283
Number of pages5
ISBN (Print)9781424466320
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010 - Kuala Lumpur, Malaysia
Duration: 12 Apr 201013 Apr 2010

Other

Other2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010
CountryMalaysia
CityKuala Lumpur
Period12/04/1013/04/10

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