A phase-locked loop reference spur modelling using simulink

Noorfazila Kamal; Said Al-Sarawi; Neil H E Weste; Derek Abbott

doi:10.1109/ICEDSA.2010.5503058

A phase-locked loop reference spur modelling using simulink

Noorfazila Kamal^*, Said Al-Sarawi, Neil H E Weste, Derek Abbott

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

5 Citations (Scopus)

Abstract

Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.

Original language	English
Title of host publication	2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	279-283
Number of pages	5
ISBN (Print)	9781424466320
DOIs	https://doi.org/10.1109/ICEDSA.2010.5503058
Publication status	Published - 2010
Externally published	Yes
Event	2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010 - Kuala Lumpur, Malaysia Duration: 12 Apr 2010 → 13 Apr 2010

Other

Other	2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010
Country/Territory	Malaysia
City	Kuala Lumpur
Period	12/04/10 → 13/04/10

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10.1109/ICEDSA.2010.5503058

Cite this

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title = "A phase-locked loop reference spur modelling using simulink",

abstract = "Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.",

author = "Noorfazila Kamal and Said Al-Sarawi and Weste, {Neil H E} and Derek Abbott",

year = "2010",

doi = "10.1109/ICEDSA.2010.5503058",

language = "English",

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pages = "279--283",

booktitle = "2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010 ; Conference date: 12-04-2010 Through 13-04-2010",

}

Kamal, N, Al-Sarawi, S, Weste, NHE & Abbott, D 2010, A phase-locked loop reference spur modelling using simulink. in 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings., 5503058, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 279-283, 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010, Kuala Lumpur, Malaysia, 12/04/10. https://doi.org/10.1109/ICEDSA.2010.5503058

A phase-locked loop reference spur modelling using simulink. / Kamal, Noorfazila; Al-Sarawi, Said; Weste, Neil H E et al.
2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings. Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE), 2010. p. 279-283 5503058.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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T1 - A phase-locked loop reference spur modelling using simulink

AU - Kamal, Noorfazila

AU - Al-Sarawi, Said

AU - Weste, Neil H E

AU - Abbott, Derek

PY - 2010

Y1 - 2010

N2 - Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.

AB - Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.

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BT - 2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings

PB - Institute of Electrical and Electronics Engineers (IEEE)

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A phase-locked loop reference spur modelling using simulink

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