A power-efficient 5.6-GHz process-compensated CMOS frequency divider

Ivan Siu Chuang Lu, Neil Weste, Sri Parameswaran

    Research output: Contribution to journalArticlepeer-review

    4 Citations (Scopus)


    This brief presents a robust, power efficient CMOS frequency divider for the 5-GHz UNII band. The divider operates as a voltage controlled ring oscillator with the output frequency modulated by the switching of the input transmission gate. The divider, designed in a 0.25-mu m SOS-CMOS technology, occupies 35 x 25 mu m(2) and exhibit a operating frequency of 5.6 GHz while consuming 79 mu W at a supply voltage of 0.8 V. Process and temperature tolerant operation can be achieved by utilizing a novel compensation circuitry to calibrate the speed of the ring oscillator-based divider. The simple compensation circuitry contains low-speed digital logic and dissipates minimal additional power since it is powered on only during the one-time factory calibration sequence.

    Original languageEnglish
    Pages (from-to)323-327
    Number of pages5
    JournalIEEE Transactions on Circuits and Systems II: Express Briefs
    Issue number4
    Publication statusPublished - Apr 2007


    • controllable delay element (CDE)
    • frequency divider
    • process compensation


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