A resistive DAC for a multi-stage sigma-delta modulator DAC with dynamic element matching

Astria Nur Irfansyah, Torsten Lehmann, Julian Jenkins, Tianle Tong, Tara Julia Hamilton

Research output: Contribution to journalArticleResearchpeer-review

Abstract

This paper presents a study and implementation of a shunt–shunt resistive voltage divider digital-to-analog converter (DAC) for use as a multibit DAC in a multi-stage noise shaping sigma-delta modulator DAC design with dynamic element matching. This resistive DAC structure is employed to address the problem of code-dependent finite output impedance and thus aims to improve systematic linearity, while still being suitable for scaled CMOS processes. Chip measurement results from an implementation in CMOS 180 nm technology are presented. At low sampling clock frequencies, an SFDR of 71.81 dB is achieved, while at a higher sampling clock frequency of 600 MHz the SFDR is measured to be 59.73 dB, all for an OSR of 32. Our results show that low systematic nonlinearity can be achieved with this resistive DAC at low sampling frequencies, and we discuss potential enhancements to our prototype to obtain better SFDR at higher sampling rate.

LanguageEnglish
Pages109-123
Number of pages15
JournalAnalog Integrated Circuits and Signal Processing
Volume98
Issue number1
DOIs
Publication statusPublished - Jan 2019
Externally publishedYes

Fingerprint

Digital to analog conversion
Modulators
Sampling
Clocks
Voltage dividers

Keywords

  • DAC
  • Dynamic element matching
  • MASH
  • Sigma-delta

Cite this

Irfansyah, Astria Nur ; Lehmann, Torsten ; Jenkins, Julian ; Tong, Tianle ; Hamilton, Tara Julia. / A resistive DAC for a multi-stage sigma-delta modulator DAC with dynamic element matching. In: Analog Integrated Circuits and Signal Processing. 2019 ; Vol. 98, No. 1. pp. 109-123.
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A resistive DAC for a multi-stage sigma-delta modulator DAC with dynamic element matching. / Irfansyah, Astria Nur; Lehmann, Torsten; Jenkins, Julian; Tong, Tianle; Hamilton, Tara Julia.

In: Analog Integrated Circuits and Signal Processing, Vol. 98, No. 1, 01.2019, p. 109-123.

Research output: Contribution to journalArticleResearchpeer-review

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