A systolic processing element for speech recognition

Neil H.E. Weste, David J. Burr, Bryan D. Ackland

Research output: Contribution to journalConference paperpeer-review

Abstract

An integrated 16b CMOS processor designed for systolic array processing, with programmable processors, capable of performing the pattern matching required for speech recognition of up to 25,000 words per second will be described.
Original languageEnglish
Pages (from-to)274-275
Number of pages2
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume25
DOIs
Publication statusPublished - 1982
Externally publishedYes
Event1982 IEEE International solid-state circuits conference - San Francisco, United States
Duration: 10 Feb 198212 Feb 1982

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