An architecture and algorithms for a VLSI computer for back-projection image reconstruction are described. The computer consists of multiple identical back-projection processors connected in a linear array; Image pixels are pumped through the processor array, collecting at each processor a contribution to the image from one of its projections. Given one back-projection processor for each image projection, the entire reconstruction can be performed in a time comparable to that needed for sequential access of all image pixels. Implementation of a MOS VLSI back-projection processor is well advanced with working designs obtained for most processor subsystems. The processor incorporates a linear interpolator to estimate values between projection samples and accommodates non-linearity in the geometrical relationship between an image and its projection.
|Number of pages||6|
|Journal||Proceedings of SPIE - The International Society for Optical Engineering|
|Publication status||Published - 21 Apr 1986|