Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector

Sithamparanathan Kandeepan; Sam Reisenfeld

Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector

Sithamparanathan Kandeepan^*, Sam Reisenfeld

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

3 Citations (Scopus)

Abstract

The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed in this paper. In the noiseless case, unlike the traditional sine function based phase locked loops, the acquisition process of the four-quadrant arctan based phase locked loops is less tedious. We will look into the pull-in process together with a time-series analysis of the DPLL for the noiseless case. The phase-plane portrait of loop is also discussed, for both the noiseless and the noisy conditions.

Original language	English
Title of host publication	Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004
Editors	Sung Jea Ko
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	648-653
Number of pages	6
ISBN (Print)	0780386396
Publication status	Published - 2004
Externally published	Yes
Event	Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004 - Seoul, Korea, Republic of Duration: 18 Nov 2004 → 19 Nov 2004

Other

Other	Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004
Country/Territory	Korea, Republic of
City	Seoul
Period	18/11/04 → 19/11/04

Cite this

Kandeepan, Sithamparanathan ; Reisenfeld, Sam. / Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector. Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004. editor / Sung Jea Ko. Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE), 2004. pp. 648-653

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title = "Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector",

abstract = "The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed in this paper. In the noiseless case, unlike the traditional sine function based phase locked loops, the acquisition process of the four-quadrant arctan based phase locked loops is less tedious. We will look into the pull-in process together with a time-series analysis of the DPLL for the noiseless case. The phase-plane portrait of loop is also discussed, for both the noiseless and the noisy conditions.",

author = "Sithamparanathan Kandeepan and Sam Reisenfeld",

year = "2004",

language = "English",

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pages = "648--653",

editor = "Ko, {Sung Jea}",

booktitle = "Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004 ; Conference date: 18-11-2004 Through 19-11-2004",

}

Kandeepan, S & Reisenfeld, S 2004, Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector. in SJ Ko (ed.), Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004. Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 648-653, Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004, Seoul, Korea, Republic of, 18/11/04.

Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector. / Kandeepan, Sithamparanathan; Reisenfeld, Sam.
Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004. ed. / Sung Jea Ko. Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE), 2004. p. 648-653.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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AU - Kandeepan, Sithamparanathan

AU - Reisenfeld, Sam

PY - 2004

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AB - The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed in this paper. In the noiseless case, unlike the traditional sine function based phase locked loops, the acquisition process of the four-quadrant arctan based phase locked loops is less tedious. We will look into the pull-in process together with a time-series analysis of the DPLL for the noiseless case. The phase-plane portrait of loop is also discussed, for both the noiseless and the noisy conditions.

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M3 - Conference proceeding contribution

AN - SCOPUS:21444440134

SN - 0780386396

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EP - 653

BT - Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004

A2 - Ko, Sung Jea

PB - Institute of Electrical and Electronics Engineers (IEEE)

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T2 - Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004

Y2 - 18 November 2004 through 19 November 2004

ER -

Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector

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