Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector

Sithamparanathan Kandeepan*, Sam Reisenfeld

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

3 Citations (Scopus)

Abstract

The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed in this paper. In the noiseless case, unlike the traditional sine function based phase locked loops, the acquisition process of the four-quadrant arctan based phase locked loops is less tedious. We will look into the pull-in process together with a time-series analysis of the DPLL for the noiseless case. The phase-plane portrait of loop is also discussed, for both the noiseless and the noisy conditions.

Original languageEnglish
Title of host publicationProceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004
EditorsSung Jea Ko
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages648-653
Number of pages6
ISBN (Print)0780386396
Publication statusPublished - 2004
Externally publishedYes
EventProceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004 - Seoul, Korea, Republic of
Duration: 18 Nov 200419 Nov 2004

Other

OtherProceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2004
CountryKorea, Republic of
CitySeoul
Period18/11/0419/11/04

Fingerprint Dive into the research topics of 'Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector'. Together they form a unique fingerprint.

Cite this