ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends

a power and performance perspective

Ivan Siu Chuang Lu*, Neil Weste, Sri Parameswaran

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

6 Citations (Scopus)

Abstract

This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and distortion ratio (SNDR) and bit error rate (BER) were evaluated with varying degrees of front-end linearity and analog to digital converter (ADC) accuracy. The analysis and simulation results indicate two or more ADC bits are required for reliable data reception in the presence of strong interference and intermodulation distortion. In addition to BER performance, power consumption of different hardware configurations is also evaluated to form the cost function for evaluating design choices. The combined power and performance analysis indicates that starting with one-bit ADC resolutions, a substantial gain in reliability can be attained by increasing ADC resolution to two-bits or more. When the ADC resolution improves beyond three bits, front-end linearization achieves similar BER improvements to increasing the ADC accuracy, at a fraction of the power cost. As a result, linear front-end designs become significant only when high precision ADCs are utilized.

Original languageEnglish
Title of host publicationProceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Place of PublicationLos Alamitos, Calif.
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages575-580
Number of pages6
Volume2006
ISBN (Print)0769525024, 9780769525020
DOIs
Publication statusPublished - 2006
Event19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design - Hyderabad, India
Duration: 3 Jan 20067 Jan 2006

Other

Other19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
CountryIndia
CityHyderabad
Period3/01/067/01/06

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