ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective

Ivan Siu Chuang Lu; Neil Weste; Sri Parameswaran

doi:10.1109/VLSID.2006.32

ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective

Ivan Siu Chuang Lu^*, Neil Weste, Sri Parameswaran

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

8 Citations (Scopus)

Abstract

This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and distortion ratio (SNDR) and bit error rate (BER) were evaluated with varying degrees of front-end linearity and analog to digital converter (ADC) accuracy. The analysis and simulation results indicate two or more ADC bits are required for reliable data reception in the presence of strong interference and intermodulation distortion. In addition to BER performance, power consumption of different hardware configurations is also evaluated to form the cost function for evaluating design choices. The combined power and performance analysis indicates that starting with one-bit ADC resolutions, a substantial gain in reliability can be attained by increasing ADC resolution to two-bits or more. When the ADC resolution improves beyond three bits, front-end linearization achieves similar BER improvements to increasing the ADC accuracy, at a fraction of the power cost. As a result, linear front-end designs become significant only when high precision ADCs are utilized.

Original language	English
Title of host publication	Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Place of Publication	Los Alamitos, Calif.
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	575-580
Number of pages	6
Volume	2006
ISBN (Print)	0769525024, 9780769525020
DOIs	https://doi.org/10.1109/VLSID.2006.32
Publication status	Published - 2006
Event	19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design - Hyderabad, India Duration: 3 Jan 2006 → 7 Jan 2006

Other

Other	19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Country/Territory	India
City	Hyderabad
Period	3/01/06 → 7/01/06

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10.1109/VLSID.2006.32

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Lu, I. S. C., Weste, N., & Parameswaran, S. (2006). ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective. In Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (Vol. 2006, pp. 575-580). [1581518] Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/VLSID.2006.32

Lu, Ivan Siu Chuang ; Weste, Neil ; Parameswaran, Sri. / ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends : a power and performance perspective. Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design. Vol. 2006 Los Alamitos, Calif. : Institute of Electrical and Electronics Engineers (IEEE), 2006. pp. 575-580

@inproceedings{bc7a15c5e2414626b4b606b18a6f0776,

title = "ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective",

abstract = "This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and distortion ratio (SNDR) and bit error rate (BER) were evaluated with varying degrees of front-end linearity and analog to digital converter (ADC) accuracy. The analysis and simulation results indicate two or more ADC bits are required for reliable data reception in the presence of strong interference and intermodulation distortion. In addition to BER performance, power consumption of different hardware configurations is also evaluated to form the cost function for evaluating design choices. The combined power and performance analysis indicates that starting with one-bit ADC resolutions, a substantial gain in reliability can be attained by increasing ADC resolution to two-bits or more. When the ADC resolution improves beyond three bits, front-end linearization achieves similar BER improvements to increasing the ADC accuracy, at a fraction of the power cost. As a result, linear front-end designs become significant only when high precision ADCs are utilized.",

author = "Lu, {Ivan Siu Chuang} and Neil Weste and Sri Parameswaran",

year = "2006",

doi = "10.1109/VLSID.2006.32",

language = "English",

isbn = "0769525024",

volume = "2006",

pages = "575--580",

booktitle = "Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design ; Conference date: 03-01-2006 Through 07-01-2006",

}

Lu, ISC, Weste, N & Parameswaran, S 2006, ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective. in Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design. vol. 2006, 1581518, Institute of Electrical and Electronics Engineers (IEEE), Los Alamitos, Calif., pp. 575-580, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design, Hyderabad, India, 3/01/06. https://doi.org/10.1109/VLSID.2006.32

ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective. / Lu, Ivan Siu Chuang; Weste, Neil; Parameswaran, Sri.
Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design. Vol. 2006 Los Alamitos, Calif.: Institute of Electrical and Electronics Engineers (IEEE), 2006. p. 575-580 1581518.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends

T2 - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design

AU - Lu, Ivan Siu Chuang

AU - Weste, Neil

AU - Parameswaran, Sri

PY - 2006

Y1 - 2006

N2 - This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and distortion ratio (SNDR) and bit error rate (BER) were evaluated with varying degrees of front-end linearity and analog to digital converter (ADC) accuracy. The analysis and simulation results indicate two or more ADC bits are required for reliable data reception in the presence of strong interference and intermodulation distortion. In addition to BER performance, power consumption of different hardware configurations is also evaluated to form the cost function for evaluating design choices. The combined power and performance analysis indicates that starting with one-bit ADC resolutions, a substantial gain in reliability can be attained by increasing ADC resolution to two-bits or more. When the ADC resolution improves beyond three bits, front-end linearization achieves similar BER improvements to increasing the ADC accuracy, at a fraction of the power cost. As a result, linear front-end designs become significant only when high precision ADCs are utilized.

AB - This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and distortion ratio (SNDR) and bit error rate (BER) were evaluated with varying degrees of front-end linearity and analog to digital converter (ADC) accuracy. The analysis and simulation results indicate two or more ADC bits are required for reliable data reception in the presence of strong interference and intermodulation distortion. In addition to BER performance, power consumption of different hardware configurations is also evaluated to form the cost function for evaluating design choices. The combined power and performance analysis indicates that starting with one-bit ADC resolutions, a substantial gain in reliability can be attained by increasing ADC resolution to two-bits or more. When the ADC resolution improves beyond three bits, front-end linearization achieves similar BER improvements to increasing the ADC accuracy, at a fraction of the power cost. As a result, linear front-end designs become significant only when high precision ADCs are utilized.

UR - http://www.scopus.com/inward/record.url?scp=33748530981&partnerID=8YFLogxK

U2 - 10.1109/VLSID.2006.32

DO - 10.1109/VLSID.2006.32

M3 - Conference proceeding contribution

AN - SCOPUS:33748530981

SN - 0769525024

SN - 9780769525020

VL - 2006

SP - 575

EP - 580

BT - Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Los Alamitos, Calif.

Y2 - 3 January 2006 through 7 January 2006

ER -

Lu ISC, Weste N, Parameswaran S. ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective. In Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design. Vol. 2006. Los Alamitos, Calif.: Institute of Electrical and Electronics Engineers (IEEE). 2006. p. 575-580. 1581518 doi: 10.1109/VLSID.2006.32

ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective

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