An asynchronous transfer mode (ATM) stream demultiplexer and switch

John R. Haddy, David J. Skellern

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

1 Citation (Scopus)

Abstract

This paper describes the implementation of an Asynchronous Transfer Mode (ATM) stream demultiplexer that processes data at rates in excess of 200Mbit/s. The embedded RAM features of a Xilinx XC4000 series FPGA have been used to implement a Content Addressable Memory (CAM), enabling simultaneous matching of an ATM cell header to multiple different match values. The CAM has the capability of performing 16, 32-bit wide, arbitrarily bit-masked matches; yet only occupies 64 CLBs. The demultiplexer can route matched cells to any of eight destinations, in unicast, multicast or broadcast fashion. The same FPGA also implements a local microprocessor interface, and uses a single match engine, independent of the main CAM, to route in-band control communications to it.

Original languageEnglish
Title of host publicationField-Programmable Logic: Smart Applications, New Paradigms and Compilers - 6th International Workshop on Field-Programmable Logic and Applications, FPL 1996, Proceedings
Place of PublicationBerlin ; New York
PublisherSpringer, Springer Nature
Pages260-269
Number of pages10
Volume1142
ISBN (Print)9783540617303
Publication statusPublished - 1996
Event6th International Workshop on Field-Programmable Logic and Applications, FPL 1996 - Darmstadt, Germany
Duration: 23 Sep 199625 Sep 1996

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume1142
ISSN (Print)03029743
ISSN (Electronic)16113349

Other

Other6th International Workshop on Field-Programmable Logic and Applications, FPL 1996
CountryGermany
CityDarmstadt
Period23/09/9625/09/96

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