An efficient ASIC design of variable-length discrete cosine transform for HEVC

Niras C. Vayalil; Joshua Haddrill; Yinan Kong

doi:10.1109/EMS.2016.047

An efficient ASIC design of variable-length discrete cosine transform for HEVC

Niras C. Vayalil, Joshua Haddrill, Yinan Kong

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

3 Citations (Scopus)

Abstract

The latest video coding standard introduced by the joint collaborative team on video coding (JCT-VC) is known as high-efficiency video coding (HEVC) or H.265. HEVC/H.265 is mainly targeted for high-definition videos, and offer more compression than its predecessor. The discrete cosine transform (DCT) is widely used for image and video compression including HEVC. This paper proposes a variablelength DCT architecture for encoding video according to the HEVC/H.265 specifications. The architecture is optimized for most likely block sizes in ultra-high definition (UHD) video, and eliminates unnecessary complexities found in many architectures proposed. The synthesized results with Synopsys design tools show that the proposed method can encode 8K UHD videos @ 60 fps in real-Time and accomplishes more than 60% in hardware savings.

Original language	English
Title of host publication	UKSim-AMSS 2016 : Proceedings
Subtitle of host publication	10th European Modelling Symposium on Computer Modelling and Simulation: EMS 2016
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	229-233
Number of pages	5
ISBN (Electronic)	9781509049707
ISBN (Print)	9781509049721
DOIs	https://doi.org/10.1109/EMS.2016.047
Publication status	Published - 2016
Event	10th European Modelling Symposium on Computer Modelling and Simulation, UKSim-AMSS 2016 - Pisa, Italy Duration: 28 Nov 2016 → 30 Nov 2016

Other

Other	10th European Modelling Symposium on Computer Modelling and Simulation, UKSim-AMSS 2016
Country/Territory	Italy
City	Pisa
Period	28/11/16 → 30/11/16

Keywords

Discrete cosine transform (DCT)
H.265
high efficiency coding (HEVC)
high definition

Access to Document

10.1109/EMS.2016.047

Cite this

@inproceedings{d22560d8d03e451c845f0e3b26c917b5,

title = "An efficient ASIC design of variable-length discrete cosine transform for HEVC",

abstract = "The latest video coding standard introduced by the joint collaborative team on video coding (JCT-VC) is known as high-efficiency video coding (HEVC) or H.265. HEVC/H.265 is mainly targeted for high-definition videos, and offer more compression than its predecessor. The discrete cosine transform (DCT) is widely used for image and video compression including HEVC. This paper proposes a variablelength DCT architecture for encoding video according to the HEVC/H.265 specifications. The architecture is optimized for most likely block sizes in ultra-high definition (UHD) video, and eliminates unnecessary complexities found in many architectures proposed. The synthesized results with Synopsys design tools show that the proposed method can encode 8K UHD videos @ 60 fps in real-Time and accomplishes more than 60% in hardware savings.",

keywords = "Discrete cosine transform (DCT), H.265, high efficiency coding (HEVC), high definition",

author = "Vayalil, {Niras C.} and Joshua Haddrill and Yinan Kong",

year = "2016",

doi = "10.1109/EMS.2016.047",

language = "English",

isbn = "9781509049721",

pages = "229--233",

booktitle = "UKSim-AMSS 2016 : Proceedings",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "10th European Modelling Symposium on Computer Modelling and Simulation, UKSim-AMSS 2016 ; Conference date: 28-11-2016 Through 30-11-2016",

}

Vayalil, NC, Haddrill, J & Kong, Y 2016, An efficient ASIC design of variable-length discrete cosine transform for HEVC. in UKSim-AMSS 2016 : Proceedings: 10th European Modelling Symposium on Computer Modelling and Simulation: EMS 2016., 7920256, Institute of Electrical and Electronics Engineers (IEEE), pp. 229-233, 10th European Modelling Symposium on Computer Modelling and Simulation, UKSim-AMSS 2016, Pisa, Italy, 28/11/16. https://doi.org/10.1109/EMS.2016.047

An efficient ASIC design of variable-length discrete cosine transform for HEVC. / Vayalil, Niras C.; Haddrill, Joshua; Kong, Yinan.
UKSim-AMSS 2016 : Proceedings: 10th European Modelling Symposium on Computer Modelling and Simulation: EMS 2016. Institute of Electrical and Electronics Engineers (IEEE), 2016. p. 229-233 7920256.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - An efficient ASIC design of variable-length discrete cosine transform for HEVC

AU - Vayalil, Niras C.

AU - Haddrill, Joshua

AU - Kong, Yinan

PY - 2016

Y1 - 2016

N2 - The latest video coding standard introduced by the joint collaborative team on video coding (JCT-VC) is known as high-efficiency video coding (HEVC) or H.265. HEVC/H.265 is mainly targeted for high-definition videos, and offer more compression than its predecessor. The discrete cosine transform (DCT) is widely used for image and video compression including HEVC. This paper proposes a variablelength DCT architecture for encoding video according to the HEVC/H.265 specifications. The architecture is optimized for most likely block sizes in ultra-high definition (UHD) video, and eliminates unnecessary complexities found in many architectures proposed. The synthesized results with Synopsys design tools show that the proposed method can encode 8K UHD videos @ 60 fps in real-Time and accomplishes more than 60% in hardware savings.

AB - The latest video coding standard introduced by the joint collaborative team on video coding (JCT-VC) is known as high-efficiency video coding (HEVC) or H.265. HEVC/H.265 is mainly targeted for high-definition videos, and offer more compression than its predecessor. The discrete cosine transform (DCT) is widely used for image and video compression including HEVC. This paper proposes a variablelength DCT architecture for encoding video according to the HEVC/H.265 specifications. The architecture is optimized for most likely block sizes in ultra-high definition (UHD) video, and eliminates unnecessary complexities found in many architectures proposed. The synthesized results with Synopsys design tools show that the proposed method can encode 8K UHD videos @ 60 fps in real-Time and accomplishes more than 60% in hardware savings.

KW - Discrete cosine transform (DCT)

KW - H.265

KW - high efficiency coding (HEVC)

KW - high definition

UR - http://www.scopus.com/inward/record.url?scp=85020023664&partnerID=8YFLogxK

U2 - 10.1109/EMS.2016.047

DO - 10.1109/EMS.2016.047

M3 - Conference proceeding contribution

AN - SCOPUS:85020023664

SN - 9781509049721

SP - 229

EP - 233

BT - UKSim-AMSS 2016 : Proceedings

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 10th European Modelling Symposium on Computer Modelling and Simulation, UKSim-AMSS 2016

Y2 - 28 November 2016 through 30 November 2016

ER -

An efficient ASIC design of variable-length discrete cosine transform for HEVC

Abstract

Other

Keywords

Access to Document

Other files and links

Fingerprint

Cite this