Analysis of different architectures of counter based Wallace multipliers

Multiplication is one of the most commonly used operations in the signal processing algorithms. Multipliers based on Wallace reduction tree provide an area-efficient strategy for high speed multiplication. A number of modifications are proposed in the literature to optimize the speed and area of the Wallace multiplier. Counter based Wallace multipliers are proved to provide faster operation as compared to the traditional Wallace multipliers. This work proposes a number of architectures for the counter based Wallace multipliers to analyse their performance for various bit lengths. Designs are synthesized using Synopsys Design Compiler in 90 nm process technology and the post synthesis delay and power results are obtained by using Synopsys Prime Time. The proposed counter based Wallace multipliers are also compared with traditional Wallace multiplier to evaluate the energy per operation of both designs. The synthesis results shows that the Power-Delay Product of the counter based Wallace multiplier is up to 17% lower as compared to the traditional Wallace multiplier.