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BSIM-CMG: Standard FinFET compact model for advanced circuit design

Juan P. Duarte, Sourabh Khandelwal, Aditya Medury, Chenming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh S. Chauhan

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

Abstract

This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG model's capabilities for circuit design using FinFET transistors for advanced technology nodes.

Original languageEnglish
Title of host publicationESSCIRC 2015
Subtitle of host publicationProceedings of the 41st European Solid-State Circuits Conference
EditorsWolfgang Pribyl, Franz Dielacher, Gernot Hueber
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages196-201
Number of pages6
ISBN (Electronic)9781467374729
ISBN (Print)9781467374705
DOIs
Publication statusPublished - 30 Oct 2015
Externally publishedYes
Event41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
Duration: 14 Sept 201518 Sept 2015

Publication series

NameProceedings of ESSCIRC
PublisherIEEE
ISSN (Electronic)1930-8833

Other

Other41st European Solid-State Circuits Conference, ESSCIRC 2015
Country/TerritoryAustria
CityGraz
Period14/09/1518/09/15

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