CAD models of losses for slotline on multilayered dielectric substrates

Payal Majumdar, A. K. Verma

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

Abstract

This paper addresses an accurate CAD oriented integrated closed-form model for the computation of losses for planar and non-planar slotline on a finite-thickness multilayered dielectric substrates. The analysis of the structures has been done using conformal mapping and single layer reduction (SLR) technique. The validity of the proposed integrated model is tested over wide range of parameters: 1 GHz ≤ f ≤ 60 GHz, 0 μm ≤ t ≤ 50 μm, 2.2 ≤ ϵr ≤ 20 and 0.02 ≤ w/h ≤ 1.0 against the 3D-EM simulated results. The average deviation of the model against the comparison is 3.4%.

Original languageEnglish
Title of host publication2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages3277-3282
Number of pages6
ISBN (Electronic)9781509060931
DOIs
Publication statusPublished - 3 Nov 2016
Event2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Shanghai, China
Duration: 8 Aug 201611 Aug 2016

Other

Other2016 Progress In Electromagnetics Research Symposium, PIERS 2016
CountryChina
CityShanghai
Period8/08/1611/08/16

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  • Cite this

    Majumdar, P., & Verma, A. K. (2016). CAD models of losses for slotline on multilayered dielectric substrates. In 2016 Progress In Electromagnetics Research Symposium, PIERS 2016 - Proceedings (pp. 3277-3282). [7735282] Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/PIERS.2016.7735282