CAD tools for automatic chip assembly based on an hierarchical design methodology including top-down floorplanning and bottom-up assembly are presented. The management of interconnect leading to area efficient designs is discussed. The benefits of automatic chip assembly are illustrated by parallel multiplier and CORDIC vector rotation circuit examples presented in a simple, hierarchical chip assembly language. The chip assemblers' support for simulation is described.
|Title of host publication||National Conference Publication - Institution of Engineers, Australia|
|Subtitle of host publication||Electronics, the enabling technologies : Microelectronics Conference VLSI 1987, Melbourne|
|Place of Publication||Barton, ACT|
|Publisher||Inst of Engineers|
|Number of pages||6|
|Publication status||Published - 1987|