CAD tools for custom VLSI assembly with applications

D. J. Coggins*, D. J. Skellern, A. Dunn, P. Allworth

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

1 Citation (Scopus)

Abstract

CAD tools for automatic chip assembly based on an hierarchical design methodology including top-down floorplanning and bottom-up assembly are presented. The management of interconnect leading to area efficient designs is discussed. The benefits of automatic chip assembly are illustrated by parallel multiplier and CORDIC vector rotation circuit examples presented in a simple, hierarchical chip assembly language. The chip assemblers' support for simulation is described.

Original languageEnglish
Title of host publicationNational Conference Publication - Institution of Engineers, Australia
Subtitle of host publicationElectronics, the enabling technologies : Microelectronics Conference VLSI 1987, Melbourne
Place of PublicationBarton, ACT
PublisherInst of Engineers
Pages73-78
Number of pages6
ISBN (Print)0858253461
Publication statusPublished - 1987
Externally publishedYes

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