Chip for back-projection image reconstruction

D. J. Skellern*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review


An SIMD back-projection computer which uses a single-chip, custom, nMOS processor in each of the parallel data paths is described. The operation of the processor is explained and some design factors which have influenced its functional definition and architecture are discussed. A draft floorplan for the chip is presented. Some sections of the chip have been successfully fabricated and tested.

Original languageEnglish
Title of host publicationIREECON International (Convention Digest) (Institution of Radio and Electronics Engineers Australia)
Place of PublicationSydney, NSW
PublisherInst of Radio & Electronics Engineers Australia
Number of pages3
Publication statusPublished - 1983
Externally publishedYes


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