An SIMD back-projection computer which uses a single-chip, custom, nMOS processor in each of the parallel data paths is described. The operation of the processor is explained and some design factors which have influenced its functional definition and architecture are discussed. A draft floorplan for the chip is presented. Some sections of the chip have been successfully fabricated and tested.
|Title of host publication||IREECON International (Convention Digest) (Institution of Radio and Electronics Engineers Australia)|
|Place of Publication||Sydney, NSW|
|Publisher||Inst of Radio & Electronics Engineers Australia|
|Number of pages||3|
|Publication status||Published - 1983|