Circuit model for double-energy-level trap centers in GaN HEMTs

Measurement results performed on a GaN high-electron-mobility transistor that show the presence of a double-energy-level (DEL) trap center in the device are presented. A novel, yet simple, circuit implementation of a DEL trap center in an FET is presented that is immediately extendable to a trap center with more than two energy levels. The model is based on the Shockley-Read-Hall statistics of the trapping process. The implementation is suitable for both time-domain and harmonic-balance simulations. Simulation results validate the proposed model.