Circuit model for single-energy-level trap centers in FETs

Sayed Ali Albahrani*, Anthony Parker, Michael Heimlich

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


A circuit implementation of a single-energy-level trap center in an FET is presented. When included in transistor models it explains the temperature-potential-dependent time constants seen in the circuit manifestations of charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time-domain and harmonic-balance simulations. The proposed model is based on the Shockley-Read-Hall (SRH) statistics of the trapping process. The results of isothermal pulse measurements performed on a GaN HEMT are presented. These measurement allow characterizing charge trapping in isolation from the effect of self-heating. These results are used to obtain the parameters of the proposed model.

Original languageEnglish
Pages (from-to)143-151
Number of pages9
JournalSolid-State Electronics
Publication statusPublished - 1 Dec 2016


  • GaN HEMT
  • Microwave FET
  • Semiconductor device measurement
  • Semiconductor device modeling
  • Trapping


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