TY - JOUR
T1 - Circuit model for single-energy-level trap centers in FETs
AU - Albahrani, Sayed Ali
AU - Parker, Anthony
AU - Heimlich, Michael
PY - 2016/12/1
Y1 - 2016/12/1
N2 - A circuit implementation of a single-energy-level trap center in an FET is presented. When included in transistor models it explains the temperature-potential-dependent time constants seen in the circuit manifestations of charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time-domain and harmonic-balance simulations. The proposed model is based on the Shockley-Read-Hall (SRH) statistics of the trapping process. The results of isothermal pulse measurements performed on a GaN HEMT are presented. These measurement allow characterizing charge trapping in isolation from the effect of self-heating. These results are used to obtain the parameters of the proposed model.
AB - A circuit implementation of a single-energy-level trap center in an FET is presented. When included in transistor models it explains the temperature-potential-dependent time constants seen in the circuit manifestations of charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time-domain and harmonic-balance simulations. The proposed model is based on the Shockley-Read-Hall (SRH) statistics of the trapping process. The results of isothermal pulse measurements performed on a GaN HEMT are presented. These measurement allow characterizing charge trapping in isolation from the effect of self-heating. These results are used to obtain the parameters of the proposed model.
KW - GaN HEMT
KW - Microwave FET
KW - Semiconductor device measurement
KW - Semiconductor device modeling
KW - Trapping
UR - http://www.scopus.com/inward/record.url?scp=84993947018&partnerID=8YFLogxK
U2 - 10.1016/j.sse.2016.08.005
DO - 10.1016/j.sse.2016.08.005
M3 - Article
AN - SCOPUS:84993947018
SN - 0038-1101
VL - 126
SP - 143
EP - 151
JO - Solid-State Electronics
JF - Solid-State Electronics
ER -