Circuit performance analysis of negative capacitance FinFETs

S. Khandelwal, A. I. Khan, J. P. Duarte, A. B. Sachid, S. Salahuddin, C. Hu

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

32 Citations (Scopus)

Abstract

Circuit-level performance analysis of negative capacitance FinFETs (NC-FinFET) is presented for ultra-low power high performance applications. Circuit simulations are performed by developing a compact model which solves Landau-Khalatnikov (L-K) equations self-consistently with the three-dimensional device electrostatics of the FinFET device. Using an accurate Lg = 30 nm FinFET model, L-K model parameters of ferroelectric (FE) layer are extracted from an experimental NC-FinFET data. With the experimentally calibrated model, we show for the first time that for the same inverter delay as the 14 nm ITRS FinFET, Vdd for NC-FinFET can be lowered from 0.7 V to 0.25 V, reducing energy by ∼10×. Optimization of the FE layer parameters can further boost the device performance.

Original languageEnglish
Title of host publication2016 Symposium on VLSI Technology
Subtitle of host publicationdigest of technical papers
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1-2
Number of pages2
ISBN (Electronic)9781509006373
DOIs
Publication statusPublished - 21 Sep 2016
Externally publishedYes
Event36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, United States
Duration: 13 Jun 201616 Jun 2016

Other

Other36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
CountryUnited States
CityHonolulu
Period13/06/1616/06/16

Fingerprint

Dive into the research topics of 'Circuit performance analysis of negative capacitance FinFETs'. Together they form a unique fingerprint.

Cite this