Circuit performance analysis of negative capacitance FinFETs

S. Khandelwal; A. I. Khan; J. P. Duarte; A. B. Sachid; S. Salahuddin; C. Hu

doi:10.1109/VLSIT.2016.7573446

Circuit performance analysis of negative capacitance FinFETs

S. Khandelwal, A. I. Khan, J. P. Duarte, A. B. Sachid, S. Salahuddin, C. Hu

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

39 Citations (Scopus)

Abstract

Circuit-level performance analysis of negative capacitance FinFETs (NC-FinFET) is presented for ultra-low power high performance applications. Circuit simulations are performed by developing a compact model which solves Landau-Khalatnikov (L-K) equations self-consistently with the three-dimensional device electrostatics of the FinFET device. Using an accurate L_g = 30 nm FinFET model, L-K model parameters of ferroelectric (FE) layer are extracted from an experimental NC-FinFET data. With the experimentally calibrated model, we show for the first time that for the same inverter delay as the 14 nm ITRS FinFET, V_dd for NC-FinFET can be lowered from 0.7 V to 0.25 V, reducing energy by ∼10×. Optimization of the FE layer parameters can further boost the device performance.

Original language	English
Title of host publication	2016 Symposium on VLSI Technology
Subtitle of host publication	digest of technical papers
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1-2
Number of pages	2
ISBN (Electronic)	9781509006373
DOIs	https://doi.org/10.1109/VLSIT.2016.7573446
Publication status	Published - 21 Sept 2016
Externally published	Yes
Event	36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, United States Duration: 13 Jun 2016 → 16 Jun 2016

Other

Other	36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
Country/Territory	United States
City	Honolulu
Period	13/06/16 → 16/06/16

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10.1109/VLSIT.2016.7573446

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title = "Circuit performance analysis of negative capacitance FinFETs",

abstract = "Circuit-level performance analysis of negative capacitance FinFETs (NC-FinFET) is presented for ultra-low power high performance applications. Circuit simulations are performed by developing a compact model which solves Landau-Khalatnikov (L-K) equations self-consistently with the three-dimensional device electrostatics of the FinFET device. Using an accurate Lg = 30 nm FinFET model, L-K model parameters of ferroelectric (FE) layer are extracted from an experimental NC-FinFET data. With the experimentally calibrated model, we show for the first time that for the same inverter delay as the 14 nm ITRS FinFET, Vdd for NC-FinFET can be lowered from 0.7 V to 0.25 V, reducing energy by ∼10×. Optimization of the FE layer parameters can further boost the device performance.",

author = "S. Khandelwal and Khan, {A. I.} and Duarte, {J. P.} and Sachid, {A. B.} and S. Salahuddin and C. Hu",

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language = "English",

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note = "36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 ; Conference date: 13-06-2016 Through 16-06-2016",

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Khandelwal, S, Khan, AI, Duarte, JP, Sachid, AB, Salahuddin, S & Hu, C 2016, Circuit performance analysis of negative capacitance FinFETs. in 2016 Symposium on VLSI Technology: digest of technical papers. Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 1-2, 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016, Honolulu, United States, 13/06/16. https://doi.org/10.1109/VLSIT.2016.7573446

Circuit performance analysis of negative capacitance FinFETs. / Khandelwal, S.; Khan, A. I.; Duarte, J. P. et al.
2016 Symposium on VLSI Technology: digest of technical papers. Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE), 2016. p. 1-2.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - Circuit performance analysis of negative capacitance FinFETs

AU - Khandelwal, S.

AU - Khan, A. I.

AU - Duarte, J. P.

AU - Sachid, A. B.

AU - Salahuddin, S.

AU - Hu, C.

PY - 2016/9/21

Y1 - 2016/9/21

N2 - Circuit-level performance analysis of negative capacitance FinFETs (NC-FinFET) is presented for ultra-low power high performance applications. Circuit simulations are performed by developing a compact model which solves Landau-Khalatnikov (L-K) equations self-consistently with the three-dimensional device electrostatics of the FinFET device. Using an accurate Lg = 30 nm FinFET model, L-K model parameters of ferroelectric (FE) layer are extracted from an experimental NC-FinFET data. With the experimentally calibrated model, we show for the first time that for the same inverter delay as the 14 nm ITRS FinFET, Vdd for NC-FinFET can be lowered from 0.7 V to 0.25 V, reducing energy by ∼10×. Optimization of the FE layer parameters can further boost the device performance.

AB - Circuit-level performance analysis of negative capacitance FinFETs (NC-FinFET) is presented for ultra-low power high performance applications. Circuit simulations are performed by developing a compact model which solves Landau-Khalatnikov (L-K) equations self-consistently with the three-dimensional device electrostatics of the FinFET device. Using an accurate Lg = 30 nm FinFET model, L-K model parameters of ferroelectric (FE) layer are extracted from an experimental NC-FinFET data. With the experimentally calibrated model, we show for the first time that for the same inverter delay as the 14 nm ITRS FinFET, Vdd for NC-FinFET can be lowered from 0.7 V to 0.25 V, reducing energy by ∼10×. Optimization of the FE layer parameters can further boost the device performance.

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M3 - Conference proceeding contribution

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SP - 1

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BT - 2016 Symposium on VLSI Technology

PB - Institute of Electrical and Electronics Engineers (IEEE)

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T2 - 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016

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ER -

Circuit performance analysis of negative capacitance FinFETs

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