Abstract
A program is described which is capable of deriving the node table, transistor parameters and parasitic effects for a MOS circuit displayed on the graphics monitor. The output format of this program is in a form suitable for direct input to a general circuit analysis program. The algorithms which use a topological mapping approach shown to have possible execution time benefits over previous methods while maintaining the overwhelming advantage of user interaction. The relationship of this approach to more automated systems is also treated.
Original language | English |
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Title of host publication | Proceedings of the 15th Design Automation Conference |
Place of Publication | Piscataway, N.J. |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 199-205 |
Number of pages | 7 |
Volume | 15 |
DOIs | |
Publication status | Published - 1978 |
Externally published | Yes |
Event | 15th Design Automation Conference - Las Vegas, United States Duration: 19 Jun 1978 → 21 Jun 1978 |
Conference
Conference | 15th Design Automation Conference |
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Country/Territory | United States |
City | Las Vegas |
Period | 19/06/78 → 21/06/78 |