Abstract
A diverse variety of algorithms and architectures for modular multiplication have been published. This paper concentrates on 2 algorithms, Montgomery and Barrett, and provides area and timing results for FPGA implementations of different architectures and wordlengths. The results show that techniques such as quotient pipelining and trivial quotient digit selection are not well suited to FPGA implementations, but that high-radix, separated modular multipliers perform well on this platform.
Original language | English |
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Title of host publication | Conference Record of the 40th Asilomar Conference on Signals, Systems and Computers, ACSSC '06 |
Place of Publication | Piscataway, NJ |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 1687-1691 |
Number of pages | 5 |
ISBN (Print) | 1424407850, 9781424407859 |
DOIs | |
Publication status | Published - 2006 |
Externally published | Yes |
Event | 40th Asilomar Conference on Signals, Systems, and Computers, ACSSC '06 - Pacific Grove, CA, United States Duration: 29 Oct 2006 → 1 Nov 2006 |
Other
Other | 40th Asilomar Conference on Signals, Systems, and Computers, ACSSC '06 |
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Country | United States |
City | Pacific Grove, CA |
Period | 29/10/06 → 1/11/06 |