TY - GEN
T1 - Comparison of Montgomery and Barrett modular multipliers on FPGAs
AU - Kong, Yinan
AU - Phillips, Braden
N1 - Copyright 2006 IEEE. Reprinted from Conference record of the Thirty-Eighth Asilomar Conference on Signals, Systems & Computers : October 29 - November 1, 2006, Pacific Grove, California. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Macquarie University’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
PY - 2006
Y1 - 2006
N2 - A diverse variety of algorithms and architectures for modular multiplication have been published. This paper concentrates on 2 algorithms, Montgomery and Barrett, and provides area and timing results for FPGA implementations of different architectures and wordlengths. The results show that techniques such as quotient pipelining and trivial quotient digit selection are not well suited to FPGA implementations, but that high-radix, separated modular multipliers perform well on this platform.
AB - A diverse variety of algorithms and architectures for modular multiplication have been published. This paper concentrates on 2 algorithms, Montgomery and Barrett, and provides area and timing results for FPGA implementations of different architectures and wordlengths. The results show that techniques such as quotient pipelining and trivial quotient digit selection are not well suited to FPGA implementations, but that high-radix, separated modular multipliers perform well on this platform.
UR - http://www.scopus.com/inward/record.url?scp=47049086345&partnerID=8YFLogxK
U2 - 10.1109/ACSSC.2006.355048
DO - 10.1109/ACSSC.2006.355048
M3 - Conference proceeding contribution
AN - SCOPUS:47049086345
SN - 1424407850
SN - 9781424407859
SP - 1687
EP - 1691
BT - Conference Record of the 40th Asilomar Conference on Signals, Systems and Computers, ACSSC '06
PB - Institute of Electrical and Electronics Engineers (IEEE)
CY - Piscataway, NJ
T2 - 40th Asilomar Conference on Signals, Systems, and Computers, ACSSC '06
Y2 - 29 October 2006 through 1 November 2006
ER -