Comparison of Montgomery and Barrett modular multipliers on FPGAs

Yinan Kong; Braden Phillips

doi:10.1109/ACSSC.2006.355048

Comparison of Montgomery and Barrett modular multipliers on FPGAs

Yinan Kong^*, Braden Phillips

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution

3 Citations (Scopus)

445 Downloads (Pure)

Abstract

A diverse variety of algorithms and architectures for modular multiplication have been published. This paper concentrates on 2 algorithms, Montgomery and Barrett, and provides area and timing results for FPGA implementations of different architectures and wordlengths. The results show that techniques such as quotient pipelining and trivial quotient digit selection are not well suited to FPGA implementations, but that high-radix, separated modular multipliers perform well on this platform.

Original language	English
Title of host publication	Conference Record of the 40th Asilomar Conference on Signals, Systems and Computers, ACSSC '06
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1687-1691
Number of pages	5
ISBN (Print)	1424407850, 9781424407859
DOIs	https://doi.org/10.1109/ACSSC.2006.355048
Publication status	Published - 2006
Externally published	Yes
Event	40th Asilomar Conference on Signals, Systems, and Computers, ACSSC '06 - Pacific Grove, CA, United States Duration: 29 Oct 2006 → 1 Nov 2006

Other

Other	40th Asilomar Conference on Signals, Systems, and Computers, ACSSC '06
Country	United States
City	Pacific Grove, CA
Period	29/10/06 → 1/11/06

Bibliographical note

Copyright 2006 IEEE. Reprinted from Conference record of the Thirty-Eighth Asilomar Conference on Signals, Systems & Computers : October 29 - November 1, 2006, Pacific Grove, California. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Macquarie Universityâ€™s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

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10.1109/ACSSC.2006.355048

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Cite this

@inproceedings{1c6da09e716e4d3486742dd28a54257c,

title = "Comparison of Montgomery and Barrett modular multipliers on FPGAs",

abstract = "A diverse variety of algorithms and architectures for modular multiplication have been published. This paper concentrates on 2 algorithms, Montgomery and Barrett, and provides area and timing results for FPGA implementations of different architectures and wordlengths. The results show that techniques such as quotient pipelining and trivial quotient digit selection are not well suited to FPGA implementations, but that high-radix, separated modular multipliers perform well on this platform.",

author = "Yinan Kong and Braden Phillips",

note = "Copyright 2006 IEEE. Reprinted from Conference record of the Thirty-Eighth Asilomar Conference on Signals, Systems & Computers : October 29 - November 1, 2006, Pacific Grove, California. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Macquarie University{\^a}€™s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.",

year = "2006",

doi = "10.1109/ACSSC.2006.355048",

language = "English",

isbn = "1424407850",

pages = "1687--1691",

booktitle = "Conference Record of the 40th Asilomar Conference on Signals, Systems and Computers, ACSSC '06",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

Kong, Y & Phillips, B 2006, Comparison of Montgomery and Barrett modular multipliers on FPGAs. in Conference Record of the 40th Asilomar Conference on Signals, Systems and Computers, ACSSC '06., 4176858, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 1687-1691, 40th Asilomar Conference on Signals, Systems, and Computers, ACSSC '06, Pacific Grove, CA, United States, 29/10/06. https://doi.org/10.1109/ACSSC.2006.355048

Comparison of Montgomery and Barrett modular multipliers on FPGAs. / Kong, Yinan; Phillips, Braden.

Conference Record of the 40th Asilomar Conference on Signals, Systems and Computers, ACSSC '06. Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE), 2006. p. 1687-1691 4176858.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution

TY - GEN

T1 - Comparison of Montgomery and Barrett modular multipliers on FPGAs

AU - Kong, Yinan

AU - Phillips, Braden

N1 - Copyright 2006 IEEE. Reprinted from Conference record of the Thirty-Eighth Asilomar Conference on Signals, Systems & Computers : October 29 - November 1, 2006, Pacific Grove, California. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Macquarie Universityâ€™s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

PY - 2006

Y1 - 2006

N2 - A diverse variety of algorithms and architectures for modular multiplication have been published. This paper concentrates on 2 algorithms, Montgomery and Barrett, and provides area and timing results for FPGA implementations of different architectures and wordlengths. The results show that techniques such as quotient pipelining and trivial quotient digit selection are not well suited to FPGA implementations, but that high-radix, separated modular multipliers perform well on this platform.

AB - A diverse variety of algorithms and architectures for modular multiplication have been published. This paper concentrates on 2 algorithms, Montgomery and Barrett, and provides area and timing results for FPGA implementations of different architectures and wordlengths. The results show that techniques such as quotient pipelining and trivial quotient digit selection are not well suited to FPGA implementations, but that high-radix, separated modular multipliers perform well on this platform.

UR - http://www.scopus.com/inward/record.url?scp=47049086345&partnerID=8YFLogxK

U2 - 10.1109/ACSSC.2006.355048

DO - 10.1109/ACSSC.2006.355048

M3 - Conference proceeding contribution

SN - 1424407850

SN - 9781424407859

SP - 1687

EP - 1691

BT - Conference Record of the 40th Asilomar Conference on Signals, Systems and Computers, ACSSC '06

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Piscataway, NJ

ER -