Compensation of 2nd harmonic distortion in 4-FET linearised transcondutor circuit

A. E. Parker*, D. G. Haigh

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

    Abstract

    In this paper, a method of compensation for the 2nd harmonic distortion of a-4-FET linearized transconductor circuit is proposed and evaluated. The sensitivity of the 2nd harmonic distortion level to the compensation parameters is evaluated. Taking account of integrated circuit process parameters, it is concluded that compensation is possible for wide bandwidths up to a decade in frequency. As a first step in understanding the mechanism causing distortion in the circuit, an expression and set of curves showing the effect of signal mismatch in a FET-pair is presented but we identify the fact that further work is needed.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    Place of PublicationPiscataway, N.J.
    PublisherInstitute of Electrical and Electronics Engineers (IEEE)
    Pages1089-1092
    Number of pages4
    Volume2
    ISBN (Print)0780312813
    DOIs
    Publication statusPublished - May 1993
    EventProceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA
    Duration: 3 May 19936 May 1993

    Other

    OtherProceedings of the 1993 IEEE International Symposium on Circuits and Systems
    CityChicago, IL, USA
    Period3/05/936/05/93

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