Abstract
In this paper, a method of compensation for the 2nd harmonic distortion of a-4-FET linearized transconductor circuit is proposed and evaluated. The sensitivity of the 2nd harmonic distortion level to the compensation parameters is evaluated. Taking account of integrated circuit process parameters, it is concluded that compensation is possible for wide bandwidths up to a decade in frequency. As a first step in understanding the mechanism causing distortion in the circuit, an expression and set of curves showing the effect of signal mismatch in a FET-pair is presented but we identify the fact that further work is needed.
Original language | English |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
Place of Publication | Piscataway, N.J. |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 1089-1092 |
Number of pages | 4 |
Volume | 2 |
ISBN (Print) | 0780312813 |
DOIs | |
Publication status | Published - May 1993 |
Event | Proceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA Duration: 3 May 1993 → 6 May 1993 |
Other
Other | Proceedings of the 1993 IEEE International Symposium on Circuits and Systems |
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City | Chicago, IL, USA |
Period | 3/05/93 → 6/05/93 |