Design of a power-aware digital image rejection receiver

Ediz Cetin; Izzet Kale; Richard C S Morling

doi:10.1109/ISCAS.2009.5117722

Design of a power-aware digital image rejection receiver

Ediz Cetin^*, Izzet Kale, Richard C S Morling

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

Abstract

This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the Image-Rejection-Ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

Original language	English
Title of host publication	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Place of Publication	Piscataway, New Jersey
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	209-212
Number of pages	4
ISBN (Print)	9781424438280
DOIs	https://doi.org/10.1109/ISCAS.2009.5117722
Publication status	Published - 2009
Externally published	Yes
Event	2009 IEEE International Symposium on Circuits and Systems, ISCAS - 2009 - Taipei, Taiwan Duration: 24 May 2009 → 27 May 2009

Other

Other	2009 IEEE International Symposium on Circuits and Systems, ISCAS - 2009
Country/Territory	Taiwan
City	Taipei
Period	24/05/09 → 27/05/09

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10.1109/ISCAS.2009.5117722

Cite this

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title = "Design of a power-aware digital image rejection receiver",

abstract = "This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the Image-Rejection-Ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.",

author = "Ediz Cetin and Izzet Kale and Morling, {Richard C S}",

year = "2009",

doi = "10.1109/ISCAS.2009.5117722",

language = "English",

isbn = "9781424438280",

pages = "209--212",

booktitle = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "2009 IEEE International Symposium on Circuits and Systems, ISCAS - 2009 ; Conference date: 24-05-2009 Through 27-05-2009",

}

Cetin, E, Kale, I & Morling, RCS 2009, Design of a power-aware digital image rejection receiver. in 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5117722, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, New Jersey, pp. 209-212, 2009 IEEE International Symposium on Circuits and Systems, ISCAS - 2009, Taipei, Taiwan, 24/05/09. https://doi.org/10.1109/ISCAS.2009.5117722

Design of a power-aware digital image rejection receiver. / Cetin, Ediz; Kale, Izzet; Morling, Richard C S.
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers (IEEE), 2009. p. 209-212 5117722.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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AU - Kale, Izzet

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N2 - This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the Image-Rejection-Ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

AB - This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the Image-Rejection-Ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

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Y2 - 24 May 2009 through 27 May 2009

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Design of a power-aware digital image rejection receiver

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