Design of a power-aware digital image rejection receiver

Ediz Cetin*, Izzet Kale, Richard C S Morling

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

Abstract

This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the Image-Rejection-Ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Place of PublicationPiscataway, New Jersey
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages209-212
Number of pages4
ISBN (Print)9781424438280
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS - 2009 - Taipei, Taiwan, Province of China
Duration: 24 May 200927 May 2009

Other

Other2009 IEEE International Symposium on Circuits and Systems, ISCAS - 2009
CountryTaiwan, Province of China
CityTaipei
Period24/05/0927/05/09

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