Design of an algorithmic Wallace multiplier using high speed counters

Shahzad Asif; Yinan Kong

doi:10.1109/ICCES.2015.7393033

Design of an algorithmic Wallace multiplier using high speed counters

Shahzad Asif, Yinan Kong

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

50 Citations (Scopus)

Abstract

Wallace tree multipliers provide a power-efficient strategy for high speed multiplication. The use of high speed 7?3 counters in the Wallace tree reduction can further improve the multiplier speed. This paper presents an algorithmic approach to construct the counter based Wallace tree multipliers. The proposed algorithm can be used to implement the efficient counter based Wallace multiplier of any size suitable for FPGA or ASIC synthesis tools. The designs are synthesized in Synopsys Design Compiler using 90 nm CMOS technology. The detailed comparison of traditional and counter based Wallace multipliers is performed which shows that the counter based Wallace multiplier is up to 22% faster as compared to the traditional Wallace multiplier.

Original language	English
Title of host publication	Proceedings - 2015 10th International Conference on Computer Engineering and Systems, ICCES 2015
Editors	Wahied Gharieb Ali Abdelaal, M. Watheq El-Kharashi, Ayman M. Bahaa El-Din, Mohamad Taher, Ahmed M. Zaki
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	133-138
Number of pages	6
ISBN (Electronic)	9781467399715
DOIs	https://doi.org/10.1109/ICCES.2015.7393033
Publication status	Published - 2015
Event	10th International Conference on Computer Engineering and Systems, ICCES 2015 - Cairo, Egypt Duration: 23 Dec 2015 → 24 Dec 2015

Other

Other	10th International Conference on Computer Engineering and Systems, ICCES 2015
Country/Territory	Egypt
City	Cairo
Period	23/12/15 → 24/12/15

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10.1109/ICCES.2015.7393033

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Asif, S., & Kong, Y. (2015). Design of an algorithmic Wallace multiplier using high speed counters. In W. G. A. Abdelaal, M. W. El-Kharashi, A. M. B. El-Din, M. Taher, & A. M. Zaki (Eds.), Proceedings - 2015 10th International Conference on Computer Engineering and Systems, ICCES 2015 (pp. 133-138). Article 7393033 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ICCES.2015.7393033

Asif, Shahzad ; Kong, Yinan. / Design of an algorithmic Wallace multiplier using high speed counters. Proceedings - 2015 10th International Conference on Computer Engineering and Systems, ICCES 2015. editor / Wahied Gharieb Ali Abdelaal ; M. Watheq El-Kharashi ; Ayman M. Bahaa El-Din ; Mohamad Taher ; Ahmed M. Zaki. Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE), 2015. pp. 133-138

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title = "Design of an algorithmic Wallace multiplier using high speed counters",

abstract = "Wallace tree multipliers provide a power-efficient strategy for high speed multiplication. The use of high speed 7?3 counters in the Wallace tree reduction can further improve the multiplier speed. This paper presents an algorithmic approach to construct the counter based Wallace tree multipliers. The proposed algorithm can be used to implement the efficient counter based Wallace multiplier of any size suitable for FPGA or ASIC synthesis tools. The designs are synthesized in Synopsys Design Compiler using 90 nm CMOS technology. The detailed comparison of traditional and counter based Wallace multipliers is performed which shows that the counter based Wallace multiplier is up to 22% faster as compared to the traditional Wallace multiplier.",

author = "Shahzad Asif and Yinan Kong",

year = "2015",

doi = "10.1109/ICCES.2015.7393033",

language = "English",

pages = "133--138",

editor = "Abdelaal, {Wahied Gharieb Ali} and El-Kharashi, {M. Watheq} and El-Din, {Ayman M. Bahaa} and Mohamad Taher and Zaki, {Ahmed M.}",

booktitle = "Proceedings - 2015 10th International Conference on Computer Engineering and Systems, ICCES 2015",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "10th International Conference on Computer Engineering and Systems, ICCES 2015 ; Conference date: 23-12-2015 Through 24-12-2015",

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Asif, S & Kong, Y 2015, Design of an algorithmic Wallace multiplier using high speed counters. in WGA Abdelaal, MW El-Kharashi, AMB El-Din, M Taher & AM Zaki (eds), Proceedings - 2015 10th International Conference on Computer Engineering and Systems, ICCES 2015., 7393033, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 133-138, 10th International Conference on Computer Engineering and Systems, ICCES 2015, Cairo, Egypt, 23/12/15. https://doi.org/10.1109/ICCES.2015.7393033

Design of an algorithmic Wallace multiplier using high speed counters. / Asif, Shahzad; Kong, Yinan.
Proceedings - 2015 10th International Conference on Computer Engineering and Systems, ICCES 2015. ed. / Wahied Gharieb Ali Abdelaal; M. Watheq El-Kharashi; Ayman M. Bahaa El-Din; Mohamad Taher; Ahmed M. Zaki. Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE), 2015. p. 133-138 7393033.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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N2 - Wallace tree multipliers provide a power-efficient strategy for high speed multiplication. The use of high speed 7?3 counters in the Wallace tree reduction can further improve the multiplier speed. This paper presents an algorithmic approach to construct the counter based Wallace tree multipliers. The proposed algorithm can be used to implement the efficient counter based Wallace multiplier of any size suitable for FPGA or ASIC synthesis tools. The designs are synthesized in Synopsys Design Compiler using 90 nm CMOS technology. The detailed comparison of traditional and counter based Wallace multipliers is performed which shows that the counter based Wallace multiplier is up to 22% faster as compared to the traditional Wallace multiplier.

AB - Wallace tree multipliers provide a power-efficient strategy for high speed multiplication. The use of high speed 7?3 counters in the Wallace tree reduction can further improve the multiplier speed. This paper presents an algorithmic approach to construct the counter based Wallace tree multipliers. The proposed algorithm can be used to implement the efficient counter based Wallace multiplier of any size suitable for FPGA or ASIC synthesis tools. The designs are synthesized in Synopsys Design Compiler using 90 nm CMOS technology. The detailed comparison of traditional and counter based Wallace multipliers is performed which shows that the counter based Wallace multiplier is up to 22% faster as compared to the traditional Wallace multiplier.

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Asif S, Kong Y. Design of an algorithmic Wallace multiplier using high speed counters. In Abdelaal WGA, El-Kharashi MW, El-Din AMB, Taher M, Zaki AM, editors, Proceedings - 2015 10th International Conference on Computer Engineering and Systems, ICCES 2015. Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE). 2015. p. 133-138. 7393033 doi: 10.1109/ICCES.2015.7393033

Design of an algorithmic Wallace multiplier using high speed counters

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