Design performance and testing of a 1 GHz GaAs coder/decoder ASIC

M. L. Parrilla*, D. J. Skellern, T. M. P. Percival, P. J. Wickham

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


The high performance architecture, design methods and test results for a system that performs coding and decoding of 24B1p block-coded data are described. Both simulation and test results demonstrate operation of the system at 1 GHz. The system specification was partitioned into high-speed and low-speed sections. The high-speed section containing critical circuit paths was implemented on a GaAs standard cell ASIC. The ASIC architecture was developed not only for high performance but also for efficiency in terms of circuit area. The development of a novel architecture called the 'common-circuit approach' enabled all required functions to be implemented on a single ASIC. Design considerations for the ASIC such as delay and fanout had a major impact on the design. Delay equalisation required considerable design effort and circuit area. Asynchronous control circuits were employed to overcome problems associated with the on-chip delays. Detailed simulations using standard cell libraries supplied by the foundry were performed during the design process. The ASIC was fabricated using a source-coupled MESFET logic family that employs 1μm enhancement and depletion mode devices. External ECL circuits were used for the low-speed sections to provide two slightly different clock signals, parity violation and clock slip for block alignment.

Original languageEnglish
Pages (from-to)30-34
Number of pages5
JournalNational Conference Publication - Institution of Engineers, Australia
Issue number91 pt 5
Publication statusPublished - 1991


Dive into the research topics of 'Design performance and testing of a 1 GHz GaAs coder/decoder ASIC'. Together they form a unique fingerprint.

Cite this