Development of passive fault current limiter in parallel biasing mode

M. Iwahara*, S. C. Mukhopadhyay, N. Fujiwara, S. Yamada

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

Abstract

In this study, the possibility of development of passive fault current limiter based on permanent magnet and saturable core in parallel biasing mode is explored. The functional characteristics are analyzed by Tableau approach. The simulation results are validated by experimental results.

Original languageEnglish
Title of host publicationIEEE International Magnetics Conference, INTERMAG 1999
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
PagesAS-09-AS-09
Number of pages1
ISBN (Print)0780355555
Publication statusPublished - 1999
Externally publishedYes
Event1999 IEEE International Magnetics Conference 'Digest of Intermag 99'; Kyongju, South Korea; ; 18 May 1999 through 21 May 1999; Code 55655 - Kyongju, South Korea, Kyongju, Korea, Republic of
Duration: 18 May 199921 May 1999

Conference

Conference1999 IEEE International Magnetics Conference 'Digest of Intermag 99'; Kyongju, South Korea; ; 18 May 1999 through 21 May 1999; Code 55655
CountryKorea, Republic of
CityKyongju
Period18/05/9921/05/99

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