Distortion compensation of multi-MESFET circuits

D. R. Webster*, D. G. Haigh, A. E. Parker

*Corresponding author for this work

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

We present an analysis of a 4-FET Transconductor at medium frequencies, using a more realistic GaAs MESFET model, to calculate optimum device widths to minimize 2nd order distortion. Provisional analytical results are compared with SPICE simulations using the Parker Skellern model. A multi-FET Frequency Doubler is similarly analyzed to calculate optimum device widths for high fundamental rejection and optimum load for 3rd order distortion nulling. The high frequency degradation of the 4-FET Transconductor is discussed. Simulated performance of two high frequency distortion compensated Linearized Isolator designs, together with a variation of the Frequency Doubler, show good performance at high frequencies.

Original languageEnglish
Pages (from-to)189-192
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
Publication statusPublished - 1994
Externally publishedYes

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