Distortion compensation of multi-MESFET circuits

D. R. Webster; D. G. Haigh; A. E. Parker

Distortion compensation of multi-MESFET circuits

D. R. Webster^*, D. G. Haigh, A. E. Parker

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

We present an analysis of a 4-FET Transconductor at medium frequencies, using a more realistic GaAs MESFET model, to calculate optimum device widths to minimize 2nd order distortion. Provisional analytical results are compared with SPICE simulations using the Parker Skellern model. A multi-FET Frequency Doubler is similarly analyzed to calculate optimum device widths for high fundamental rejection and optimum load for 3rd order distortion nulling. The high frequency degradation of the 4-FET Transconductor is discussed. Simulated performance of two high frequency distortion compensated Linearized Isolator designs, together with a variation of the Frequency Doubler, show good performance at high frequencies.

Original language	English
Pages (from-to)	189-192
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
Publication status	Published - 1994
Externally published	Yes

Cite this

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title = "Distortion compensation of multi-MESFET circuits",

abstract = "We present an analysis of a 4-FET Transconductor at medium frequencies, using a more realistic GaAs MESFET model, to calculate optimum device widths to minimize 2nd order distortion. Provisional analytical results are compared with SPICE simulations using the Parker Skellern model. A multi-FET Frequency Doubler is similarly analyzed to calculate optimum device widths for high fundamental rejection and optimum load for 3rd order distortion nulling. The high frequency degradation of the 4-FET Transconductor is discussed. Simulated performance of two high frequency distortion compensated Linearized Isolator designs, together with a variation of the Frequency Doubler, show good performance at high frequencies.",

author = "Webster, \{D. R.\} and Haigh, \{D. G.\} and Parker, \{A. E.\}",

year = "1994",

language = "English",

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pages = "189--192",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

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T1 - Distortion compensation of multi-MESFET circuits

AU - Webster, D. R.

AU - Haigh, D. G.

AU - Parker, A. E.

PY - 1994

Y1 - 1994

N2 - We present an analysis of a 4-FET Transconductor at medium frequencies, using a more realistic GaAs MESFET model, to calculate optimum device widths to minimize 2nd order distortion. Provisional analytical results are compared with SPICE simulations using the Parker Skellern model. A multi-FET Frequency Doubler is similarly analyzed to calculate optimum device widths for high fundamental rejection and optimum load for 3rd order distortion nulling. The high frequency degradation of the 4-FET Transconductor is discussed. Simulated performance of two high frequency distortion compensated Linearized Isolator designs, together with a variation of the Frequency Doubler, show good performance at high frequencies.

AB - We present an analysis of a 4-FET Transconductor at medium frequencies, using a more realistic GaAs MESFET model, to calculate optimum device widths to minimize 2nd order distortion. Provisional analytical results are compared with SPICE simulations using the Parker Skellern model. A multi-FET Frequency Doubler is similarly analyzed to calculate optimum device widths for high fundamental rejection and optimum load for 3rd order distortion nulling. The high frequency degradation of the 4-FET Transconductor is discussed. Simulated performance of two high frequency distortion compensated Linearized Isolator designs, together with a variation of the Frequency Doubler, show good performance at high frequencies.

UR - https://www.scopus.com/pages/publications/0028561537

M3 - Article

AN - SCOPUS:0028561537

SN - 0271-4310

VL - 5

SP - 189

EP - 192

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

ER -

Distortion compensation of multi-MESFET circuits

Abstract

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