Double-polysilicon self-aligned lateral bipolar transistors

P. Pengpad*, D. M. Bagnall

*Corresponding author for this work

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A new lateral bipolar junction transistor that utilises a double-polysilicon self-aligned structure to maximise high-frequency performance is introduced. Silicon-on-oxide (SOI) wafers are used to isolate devices from the substrate and to minimise parasitic substrate capacitances (C JCS0) around 1.3-2.6 fF (substrate is ground). A SOI thickness of 0.2-0.5 μm combined with 0.13-0.25 μm lithography could allow a reduction of transistor dimensions down to (0.2-0.5) × (0.13-0.25) μm 2 and give an estimated minimum emitter/base junction capacitance (C JE0) of 0.54-1.36 fF. Simple device isolation is predicted to produce a small collector/base junction capacitance (C JC0) of 0.42-2.00 fF. Furthermore, use of a double base contact can help reduce base resistance (R B) to 0.43-1.17 kΩ and a wide collector window directly contacted to the collector is estimated to result in around 0.66-1.58 kΩ collector resistance (R C). By taking all parameters into account a cut-off frequency (f T) of 69-116 GHz and maximum oscillation frequency (f max) of 61-128 GHz is predicted for this design, in addition a gain of 47-101 (using minimum gain enhancement) and roughly 10.6-21.0 ps ECL propagation delay time, at a current of 0.4-1.0 mA could be achieved. Our simulations indicate that this new doubled-polysilicon self-aligned structure could outperform all other silicon bipolar transistors that have been reported.

Original languageEnglish
Pages (from-to)183-187
Number of pages5
JournalJournal of Materials Science: Materials in Electronics
Volume19
Issue number2
DOIs
Publication statusPublished - Feb 2008
Externally publishedYes

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