Double-polysilicon self-aligned sige: C lateral heterojunction bipolar transistors: design and simulation

A new design of SiGe:C lateral heterojunction bipolar transistor is introduced. The design utilises a double-polysilicon self-aligned structure to maximise the highfrequency performance of the device. Silicon-on-oxide (SOI) wafers are used to isolate devices from the substrate and to minimise parasitic substrate capacitances (CJCS0) to around 1.3-2.6fF. A SOI thickness of 0.1um combined with 0.13-0.25um lithographic resolutions provides transistors with dimensions of (0.1x0.39)um2 and (0.1x0.75)um2, respectively. These devices should provide an estimated emitter/base junction capacitance (CJE0) in the range 0.8-1.5fF, while simple device isolation is predicted to produce a small collector/base junction capacitance (CJC0) of 1.3-2.5fF. Furthermore, use of a double base contact helps to reduce the base resistance (RB) to 16-18u and a wide collector window directly contacted to the collector is estimated to result in around 16u collector resistance (RC). By taking all parameters into account a cut-off frequency (fT) of 195-395GHz and maximum oscillation frequency (fmax) of 473-983GHz are predicted for this design, in addition a gain of around 340 and1.59-2.84ps ECL propagation delay time, at a current of 4-8mA can be achieved. Our simulations indicate that this new double-polysilicon self-aligned structure could outperform all other SiGe heterojunction bipolar transistors that have been reported.