Dynamic scheduling of voter checks in FPGA-based TMR systems

Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Ediz Cetin, Oliver Diessel

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

4 Citations (Scopus)

Abstract

SRAM-based Field-Programmable Gate Arrays (FP-GAs) are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for partially reconfiguring corrupted modules of Triple Modular Redundant (TMR) FPGA-based designs have been described in the literature. Most of these techniques require some form of network-on-chip for aggregating voter error messages from the system's TMR components to a central reconfiguration controller in order to trigger the partial reconfiguration of modules when they become faulty. The frequency at which TMR components fail in the system depends on their soft-error vulnerability. However, most error recovery techniques adopt a static voter error checking schedule, which leads to delays in checking TMR components with high failure probability. In this paper we propose a Voter Scheduling Engine (VSE) for dynamically prioritizing and managing TMR voter checks so as to minimize the error detection time in the system and to thereby maximize the system's reliability. Software and hardware implementations of the VSE are proposed. Moreover, we have implemented the classic static voter checking schedule and the VSE on a real TMR system and evaluated the reliabilities of both approaches for varying radiation environments. Results demonstrate that the likelihood of system failure can be decreased by up to 50% when the VSE, rather than static voter checking, is incorporated into the TMR system.

Original languageEnglish
Title of host publicationProceedings of the 2016 International Conference on Field-Programmable Technology (FPT)
EditorsYuchen Song, Shaojun Wang, Brent Nelson, Junbao Li, Yu Peng
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages169-172
Number of pages4
ISBN (Electronic)9781509056026, 9781509056019
ISBN (Print)9781509056033
DOIs
Publication statusPublished - 2016
Externally publishedYes
Event15th International Conference on Field-Programmable Technology, FPT 2016 - Xi'an, China
Duration: 7 Dec 20169 Dec 2016

Other

Other15th International Conference on Field-Programmable Technology, FPT 2016
CountryChina
CityXi'an
Period7/12/169/12/16

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  • Cite this

    Nguyen, N. T. H., Agiakatsikas, D., Cetin, E., & Diessel, O. (2016). Dynamic scheduling of voter checks in FPGA-based TMR systems. In Y. Song, S. Wang, B. Nelson, J. Li, & Y. Peng (Eds.), Proceedings of the 2016 International Conference on Field-Programmable Technology (FPT) (pp. 169-172). [7929525] Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/FPT.2016.7929525