Dynamic Time Warp Pattern Matching Using an Integrated Multiprocessing Array

Dynamic time warping is a well-established technique for time alignment and comparison of speech and image patterns. This paper decribes the architecture, algorithms, and design of a CMOS integrated processing array used for computing the dynamic time warp algorithm. Emphasis is placed on speech recognition applications because of the real-time constraints imposed by isolated and continuous speech recognition. High throughput is obtained through the use of extensive pipelining, parallel computation, and simultaneous matching of multiple patterns. A realistic speech recognition application based on 40 nine-component linear predictor coefficient (LPC) vectors per word permits 20 000 isolated word comparisons per second or, equivalently, real time recognition of a 20 000 word vocabulary. The paper also illustrates a trend in IC design in which the architecture of the system leads to an embodiment which far outperforms solutions based on current design methodologies.