Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers

Ediz Cetin; Suleyman S. Demirsoy; Izzet Kale; Richard C S Morling

Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers

Ediz Cetin^*, Suleyman S. Demirsoy, Izzet Kale, Richard C S Morling

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

5 Citations (Scopus)

Abstract

Digital signal processing techniques for compensating the IQ-imbalances in quadrature receivers are paving the path towards software-configurable-radio- receivers. Unsupervised signal processing algorithms operating at the baseband have been developed to deal with these impairments. This paper deals with an efficient FPGA implementation of an adaptive IQ-imbalance corrector using reduced range multipliers. Use of reduced-range multipliers result in 40% reduction in area and power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier approach.

Original language	English
Title of host publication	13th European Signal Processing Conference, EUSIPCO 2005
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	2410-2413
Number of pages	4
ISBN (Print)	1604238216, 9781604238211
Publication status	Published - 2005
Externally published	Yes
Event	13th European Signal Processing Conference, EUSIPCO 2005 - Antalya, Turkey Duration: 4 Sept 2005 → 8 Sept 2005

Other

Other	13th European Signal Processing Conference, EUSIPCO 2005
Country/Territory	Turkey
City	Antalya
Period	4/09/05 → 8/09/05

Cite this

@inproceedings{4179f823360a4cfc965e7cdbe8b6e2cc,

title = "Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers",

abstract = "Digital signal processing techniques for compensating the IQ-imbalances in quadrature receivers are paving the path towards software-configurable-radio- receivers. Unsupervised signal processing algorithms operating at the baseband have been developed to deal with these impairments. This paper deals with an efficient FPGA implementation of an adaptive IQ-imbalance corrector using reduced range multipliers. Use of reduced-range multipliers result in 40% reduction in area and power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier approach.",

author = "Ediz Cetin and Demirsoy, {Suleyman S.} and Izzet Kale and Morling, {Richard C S}",

year = "2005",

language = "English",

isbn = "1604238216",

pages = "2410--2413",

booktitle = "13th European Signal Processing Conference, EUSIPCO 2005",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "13th European Signal Processing Conference, EUSIPCO 2005 ; Conference date: 04-09-2005 Through 08-09-2005",

}

Cetin, E, Demirsoy, SS, Kale, I & Morling, RCS 2005, Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers. in 13th European Signal Processing Conference, EUSIPCO 2005. Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 2410-2413, 13th European Signal Processing Conference, EUSIPCO 2005, Antalya, Turkey, 4/09/05.

Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers. / Cetin, Ediz; Demirsoy, Suleyman S.; Kale, Izzet et al.
13th European Signal Processing Conference, EUSIPCO 2005. Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE), 2005. p. 2410-2413.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers

AU - Cetin, Ediz

AU - Demirsoy, Suleyman S.

AU - Kale, Izzet

AU - Morling, Richard C S

PY - 2005

Y1 - 2005

N2 - Digital signal processing techniques for compensating the IQ-imbalances in quadrature receivers are paving the path towards software-configurable-radio- receivers. Unsupervised signal processing algorithms operating at the baseband have been developed to deal with these impairments. This paper deals with an efficient FPGA implementation of an adaptive IQ-imbalance corrector using reduced range multipliers. Use of reduced-range multipliers result in 40% reduction in area and power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier approach.

AB - Digital signal processing techniques for compensating the IQ-imbalances in quadrature receivers are paving the path towards software-configurable-radio- receivers. Unsupervised signal processing algorithms operating at the baseband have been developed to deal with these impairments. This paper deals with an efficient FPGA implementation of an adaptive IQ-imbalance corrector using reduced range multipliers. Use of reduced-range multipliers result in 40% reduction in area and power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier approach.

UR - http://www.scopus.com/inward/record.url?scp=84863652335&partnerID=8YFLogxK

M3 - Conference proceeding contribution

AN - SCOPUS:84863652335

SN - 1604238216

SN - 9781604238211

SP - 2410

EP - 2413

BT - 13th European Signal Processing Conference, EUSIPCO 2005

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Piscataway, NJ

T2 - 13th European Signal Processing Conference, EUSIPCO 2005

Y2 - 4 September 2005 through 8 September 2005

ER -

Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers

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