Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers

Ediz Cetin*, Suleyman S. Demirsoy, Izzet Kale, Richard C S Morling

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

4 Citations (Scopus)

Abstract

Digital signal processing techniques for compensating the IQ-imbalances in quadrature receivers are paving the path towards software-configurable-radio- receivers. Unsupervised signal processing algorithms operating at the baseband have been developed to deal with these impairments. This paper deals with an efficient FPGA implementation of an adaptive IQ-imbalance corrector using reduced range multipliers. Use of reduced-range multipliers result in 40% reduction in area and power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier approach.

Original languageEnglish
Title of host publication13th European Signal Processing Conference, EUSIPCO 2005
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages2410-2413
Number of pages4
ISBN (Print)1604238216, 9781604238211
Publication statusPublished - 2005
Externally publishedYes
Event13th European Signal Processing Conference, EUSIPCO 2005 - Antalya, Turkey
Duration: 4 Sep 20058 Sep 2005

Other

Other13th European Signal Processing Conference, EUSIPCO 2005
CountryTurkey
CityAntalya
Period4/09/058/09/05

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  • Cite this

    Cetin, E., Demirsoy, S. S., Kale, I., & Morling, R. C. S. (2005). Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers. In 13th European Signal Processing Conference, EUSIPCO 2005 (pp. 2410-2413). Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE).