Efficient low-power design and implementation of iq-imbalance compensator using early termination

Ediz Cetin; Izzet Kale; Richard C S Morling

Efficient low-power design and implementation of iq-imbalance compensator using early termination

Ediz Cetin^*, Izzet Kale, Richard C S Morling

^*Corresponding author for this work

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

2 Citations (Scopus)

Abstract

In this paper, we propose a low-complexity architecture for the implementation of adaptive IQ-imbalance compensation in quadrature zero-IF receivers. Our blind IQ-compensation scheme jointly compensates for IQ phase and gain errors without the need for test/pilot tones. The proposed architecture employs early-termination of the iteration process; this enables the powering-down of the parts of the adaptive algorithm thereby saving power. The complexity, in terms of power-down efficiency is evaluated and shows a reduction by 37-50% for 32-PSK and 37-58% for 64-QAM modulated signals.

Original language	English
Title of host publication	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings
Place of Publication	Piscataway, New Jersey
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	4995-4998
Number of pages	4
ISBN (Print)	0780393902, 9780780393905
Publication status	Published - 2006
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 21 May 2006 → 24 May 2006

Other

Other	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/Territory	Greece
City	Kos
Period	21/05/06 → 24/05/06

Cite this

@inproceedings{ef939e580a144aa881e70da6193ab332,

title = "Efficient low-power design and implementation of iq-imbalance compensator using early termination",

abstract = "In this paper, we propose a low-complexity architecture for the implementation of adaptive IQ-imbalance compensation in quadrature zero-IF receivers. Our blind IQ-compensation scheme jointly compensates for IQ phase and gain errors without the need for test/pilot tones. The proposed architecture employs early-termination of the iteration process; this enables the powering-down of the parts of the adaptive algorithm thereby saving power. The complexity, in terms of power-down efficiency is evaluated and shows a reduction by 37-50% for 32-PSK and 37-58% for 64-QAM modulated signals.",

author = "Ediz Cetin and Izzet Kale and Morling, {Richard C S}",

year = "2006",

language = "English",

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pages = "4995--4998",

booktitle = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",

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Cetin, E, Kale, I & Morling, RCS 2006, Efficient low-power design and implementation of iq-imbalance compensator using early termination. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693753, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, New Jersey, pp. 4995-4998, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 21/05/06.

Efficient low-power design and implementation of iq-imbalance compensator using early termination. / Cetin, Ediz; Kale, Izzet; Morling, Richard C S.
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers (IEEE), 2006. p. 4995-4998 1693753.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - Efficient low-power design and implementation of iq-imbalance compensator using early termination

AU - Cetin, Ediz

AU - Kale, Izzet

AU - Morling, Richard C S

PY - 2006

Y1 - 2006

N2 - In this paper, we propose a low-complexity architecture for the implementation of adaptive IQ-imbalance compensation in quadrature zero-IF receivers. Our blind IQ-compensation scheme jointly compensates for IQ phase and gain errors without the need for test/pilot tones. The proposed architecture employs early-termination of the iteration process; this enables the powering-down of the parts of the adaptive algorithm thereby saving power. The complexity, in terms of power-down efficiency is evaluated and shows a reduction by 37-50% for 32-PSK and 37-58% for 64-QAM modulated signals.

AB - In this paper, we propose a low-complexity architecture for the implementation of adaptive IQ-imbalance compensation in quadrature zero-IF receivers. Our blind IQ-compensation scheme jointly compensates for IQ phase and gain errors without the need for test/pilot tones. The proposed architecture employs early-termination of the iteration process; this enables the powering-down of the parts of the adaptive algorithm thereby saving power. The complexity, in terms of power-down efficiency is evaluated and shows a reduction by 37-50% for 32-PSK and 37-58% for 64-QAM modulated signals.

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M3 - Conference proceeding contribution

AN - SCOPUS:34547324251

SN - 0780393902

SN - 9780780393905

SP - 4995

EP - 4998

BT - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Piscataway, New Jersey

T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems

Y2 - 21 May 2006 through 24 May 2006

ER -

Efficient low-power design and implementation of iq-imbalance compensator using early termination

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