Experience of developing and using CAD tools for III-V FETs effectively in a nonideal world

D. R. Webster*, A. E. Parker, M. Hutabarat, G. R. Ataei, D. G. Haigh, P. Radmore

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    Abstract

    This paper describes the experience gained in developing and using CAD tools for the design of low distortion and nonlinear FET circuits using III-V technology. It includes a description of the CAD packages used, key features required in the CAD packages for realistic simulation, techniques for small and large signal "quick look" assessment for choosing bias and load and some example circuits where the tools have been used successfully.

    Original languageEnglish
    Pages (from-to)11-26
    Number of pages16
    JournalIEE Colloquium (Digest)
    Issue number64
    Publication statusPublished - 24 May 1999

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