This paper describes the experience gained in developing and using CAD tools for the design of low distortion and nonlinear FET circuits using III-V technology. It includes a description of the CAD packages used, key features required in the CAD packages for realistic simulation, techniques for small and large signal "quick look" assessment for choosing bias and load and some example circuits where the tools have been used successfully.
|Number of pages||16|
|Journal||IEE Colloquium (Digest)|
|Publication status||Published - 24 May 1999|